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From: "Mi, Dapeng" <dapeng1.mi@linux.intel.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: Ingo Molnar <mingo@redhat.com>,
	Arnaldo Carvalho de Melo <acme@kernel.org>,
	Namhyung Kim <namhyung@kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Dave Hansen <dave.hansen@linux.intel.com>,
	Ian Rogers <irogers@google.com>,
	Adrian Hunter <adrian.hunter@intel.com>,
	Jiri Olsa <jolsa@kernel.org>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Andi Kleen <ak@linux.intel.com>,
	Eranian Stephane <eranian@google.com>,
	Mark Rutland <mark.rutland@arm.com>,
	broonie@kernel.org, Ravi Bangoria <ravi.bangoria@amd.com>,
	linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
	Zide Chen <zide.chen@intel.com>,
	Falcon Thomas <thomas.falcon@intel.com>,
	Dapeng Mi <dapeng1.mi@intel.com>,
	Xudong Hao <xudong.hao@intel.com>,
	Kan Liang <kan.liang@linux.intel.com>
Subject: Re: [Patch v8 07/23] x86/fpu/xstate: Add xsaves_nmi() helper
Date: Mon, 1 Jun 2026 10:31:59 +0800	[thread overview]
Message-ID: <5f60950a-0cad-4d05-9997-3a8af307992a@linux.intel.com> (raw)
In-Reply-To: <20260529113218.GJ3493090@noisy.programming.kicks-ass.net>


On 5/29/2026 7:32 PM, Peter Zijlstra wrote:
> On Fri, May 29, 2026 at 03:56:29PM +0800, Dapeng Mi wrote:
>> From: Kan Liang <kan.liang@linux.intel.com>
>>
>> Add xsaves_nmi() to save supported xsave states in NMI handler.
>>
>> This function is similar to xsaves(), but should only be called within
>> a NMI handler. This function returns the actual register contents at
>> the moment the NMI occurs.
>>
>> Currently the perf subsystem is the sole user of this helper. It uses
>> this function to snapshot SIMD (XMM/YMM/ZMM) and APX eGPRs registers
>> which would be added in subsequent patches.
>>
>> Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
>> Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
>> ---
>>  arch/x86/include/asm/fpu/xstate.h |  1 +
>>  arch/x86/kernel/fpu/xstate.c      | 23 +++++++++++++++++++++++
>>  2 files changed, 24 insertions(+)
>>
>> diff --git a/arch/x86/include/asm/fpu/xstate.h b/arch/x86/include/asm/fpu/xstate.h
>> index 7a7dc9d56027..38fa8ff26559 100644
>> --- a/arch/x86/include/asm/fpu/xstate.h
>> +++ b/arch/x86/include/asm/fpu/xstate.h
>> @@ -110,6 +110,7 @@ int xfeature_size(int xfeature_nr);
>>  
>>  void xsaves(struct xregs_state *xsave, u64 mask);
>>  void xrstors(struct xregs_state *xsave, u64 mask);
>> +void xsaves_nmi(struct xregs_state *xsave, u64 mask);
>>  
>>  int xfd_enable_feature(u64 xfd_err);
>>  
>> diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c
>> index a7b6524a9dea..4394091c4791 100644
>> --- a/arch/x86/kernel/fpu/xstate.c
>> +++ b/arch/x86/kernel/fpu/xstate.c
>> @@ -1474,6 +1474,29 @@ void xrstors(struct xregs_state *xstate, u64 mask)
>>  	WARN_ON_ONCE(err);
>>  }
>>  
>> +/**
>> + * xsaves_nmi - Save selected components to a kernel xstate buffer in NMI
>> + * @xstate:	Pointer to the buffer
>> + * @mask:	Feature mask to select the components to save
>> + *
>> + * This function is similar to xsaves(), but should only be called within
>> + * a NMI handler. This function returns the actual register contents at
>> + * the moment the NMI occurs.
>> + *
>> + * Currently, the perf subsystem is the sole user of this helper. It uses
>> + * the function to snapshot SIMD (XMM/YMM/ZMM) and APX eGPRs registers.
>> + */
>> +void xsaves_nmi(struct xregs_state *xstate, u64 mask)
>> +{
>> +	int err;
>> +
>> +	if (!in_nmi())
>> +		return;
>> +
>> +	XSTATE_OP(XSAVES, xstate, (u32)mask, (u32)(mask >> 32), err);
>> +	WARN_ON_ONCE(err);
>> +}
> Sashiko raises a fun point vs skid; if an exclude_kernel=1 event trips
> inside the kernel this can potentially leak a whole pile of kernel regs.
>
> But of course the same thing is true for the existing setup. So perhaps
> that doesn't need to concern us now.
>
> There used to be discussions about this case, and I think we had generic
> code to sanitize such boundary events, but I can't seem to find that in
> the current tree.
>
> Mark, ISTR you were involved at some point, any idea what happened?

Just consult this question if current code has such kind of boundary check
with Gemini, his answer is no.

Currently perf_sample_regs_intr() unconditionally save the intr regs and
set the ABI, a simple way to mitigate this security risk may be like this,

diff --git a/kernel/events/core.c b/kernel/events/core.c
index 1654c493be56..e6116eab44c5 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -7920,10 +7920,21 @@ static void perf_sample_regs_user(struct perf_regs
*regs_user,
 }

 static void perf_sample_regs_intr(struct perf_regs *regs_intr,
-                                 struct pt_regs *regs)
+                                 struct pt_regs *regs,
+                                 bool exclude_kernel)
 {
-       regs_intr->regs = regs;
-       regs_intr->abi  = perf_reg_abi(current);
+       /*
+        * Hardware skid can lead to PMI is delivered after
+        * the CPU has already entered kernel mode. In that case,
+        * user-space sampling must not expose kernel register state.
+        */
+       if (exclude_kernel && !user_mode(regs)) {
+               regs_intr->abi = PERF_SAMPLE_REGS_ABI_NONE;
+               regs_intr->regs = NULL;
+       } else {
+               regs_intr->regs = regs;
+               regs_intr->abi  = perf_reg_abi(current);
+       }
 }

The PERF_SAMPLE_REGS_ABI_NONE would prevent the later code to sample and
expose the SIMD registers further. 

Thanks.


>

  reply	other threads:[~2026-06-01  2:32 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-29  7:56 [Patch v8 00/23] Support SIMD/eGPRs/SSP registers sampling for perf Dapeng Mi
2026-05-29  7:56 ` [Patch v8 01/23] perf/x86/intel: Validate return value of intel_pmu_init_hybrid() Dapeng Mi
2026-05-29 11:11   ` Peter Zijlstra
2026-06-01  1:02     ` Mi, Dapeng
2026-05-29  7:56 ` [Patch v8 02/23] perf/x86: Move hybrid PMU initialization before x86_pmu_starting_cpu() Dapeng Mi
2026-05-29  7:56 ` [Patch v8 03/23] perf/x86/intel: Enable large PEBS sampling for XMMs Dapeng Mi
2026-05-29  7:56 ` [Patch v8 04/23] perf/x86/intel: Convert x86_perf_regs to per-cpu variables Dapeng Mi
2026-05-29  7:56 ` [Patch v8 05/23] perf: Eliminate duplicate arch-specific functions definations Dapeng Mi
2026-05-29  7:56 ` [Patch v8 06/23] perf/x86: Use x86_perf_regs in the x86 nmi handlers Dapeng Mi
2026-05-29  7:56 ` [Patch v8 07/23] x86/fpu/xstate: Add xsaves_nmi() helper Dapeng Mi
2026-05-29 11:32   ` Peter Zijlstra
2026-06-01  2:31     ` Mi, Dapeng [this message]
2026-06-01  8:28       ` Peter Zijlstra
2026-05-29  7:56 ` [Patch v8 08/23] x86/fpu: Ensure TIF_NEED_FPU_LOAD is set after saving FPU state Dapeng Mi
2026-05-29  7:56 ` [Patch v8 09/23] perf: Move and enhance has_extended_regs() for arch-specific use Dapeng Mi
2026-05-29  7:56 ` [Patch v8 10/23] perf/x86: Enable XMM Register Sampling for Non-PEBS Events Dapeng Mi
2026-05-29 11:38   ` Peter Zijlstra
2026-06-01  3:04     ` Mi, Dapeng
2026-05-29  7:56 ` [Patch v8 11/23] perf/x86: Enable XMM register sampling for REGS_USER case Dapeng Mi
2026-05-29 11:42   ` Peter Zijlstra
2026-06-01  5:53     ` Mi, Dapeng
2026-05-29  7:56 ` [Patch v8 12/23] perf: Add sampling support for SIMD registers Dapeng Mi
2026-05-29  7:56 ` [Patch v8 13/23] perf/x86: Support XMM sampling using sample_simd_vec_reg_* fields Dapeng Mi
2026-05-29  7:56 ` [Patch v8 14/23] perf/x86: Support YMM " Dapeng Mi
2026-05-29  7:56 ` [Patch v8 15/23] perf/x86: Support ZMM " Dapeng Mi
2026-05-29  7:56 ` [Patch v8 16/23] perf/x86: Support OPMASK sampling using sample_simd_pred_reg_* fields Dapeng Mi
2026-05-29  7:56 ` [Patch v8 17/23] perf: Enhance perf_reg_validate() with simd_enabled argument Dapeng Mi
2026-05-29  7:56 ` [Patch v8 18/23] perf/x86: Support eGPRs sampling using sample_regs_* fields Dapeng Mi
2026-05-29  7:56 ` [Patch v8 19/23] perf/x86: Support SSP " Dapeng Mi
2026-05-29  7:56 ` [Patch v8 20/23] perf/x86/intel: Support arch-PEBS based SIMD/eGPRs/SSP sampling Dapeng Mi
2026-05-29  7:56 ` [Patch v8 21/23] perf/x86/intel: Enable PERF_PMU_CAP_SIMD_REGS capability Dapeng Mi
2026-05-29  7:56 ` [Patch v8 22/23] perf/x86: Activate back-to-back NMI detection for arch-PEBS induced NMIs Dapeng Mi
2026-05-29  7:56 ` [Patch v8 23/23] perf/x86/intel: Add sanity check for PEBS fragment size Dapeng Mi
2026-05-29  8:32 ` [Patch v8 00/23] Support SIMD/eGPRs/SSP registers sampling for perf Mi, Dapeng

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