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[130.180.211.218]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-38058b70c44sm8958669f8f.80.2024.10.28.02.44.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 28 Oct 2024 02:44:51 -0700 (PDT) Message-ID: <5f7179ec-e4ce-4644-8a60-ce407a4d2f11@linaro.org> Date: Mon, 28 Oct 2024 10:44:50 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/2] clocksource/drivers/timer-riscv: Stop stimecmp when cpu hotplug To: Nick Hu , greentime.hu@sifive.com, zong.li@sifive.com, "Rafael J. Wysocki" , Pavel Machek , Paul Walmsley , Palmer Dabbelt , Albert Ou , Thomas Gleixner , Andrew Jones , Conor Dooley , Samuel Holland , Sunil V L , linux-pm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Anup Patel References: <20241028033928.223218-1-nick.hu@sifive.com> <20241028033928.223218-3-nick.hu@sifive.com> Content-Language: en-US From: Daniel Lezcano In-Reply-To: <20241028033928.223218-3-nick.hu@sifive.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 28/10/2024 04:39, Nick Hu wrote: > Stop the timer when the cpu is going to be offline otherwise the > timer interrupt may be pending while performing power-down. > > Suggested-by: Anup Patel > Link: https://lore.kernel.org/lkml/20240829033904.477200-3-nick.hu@sifive.com/T/#u > Signed-off-by: Nick Hu > Reviewed-by: Anup Patel > --- > drivers/clocksource/timer-riscv.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c > index 48ce50c5f5e6..166dee14e46b 100644 > --- a/drivers/clocksource/timer-riscv.c > +++ b/drivers/clocksource/timer-riscv.c > @@ -127,6 +127,12 @@ static int riscv_timer_starting_cpu(unsigned int cpu) > static int riscv_timer_dying_cpu(unsigned int cpu) > { > disable_percpu_irq(riscv_clock_event_irq); > + /* > + * Stop the timer when the cpu is going to be offline otherwise > + * the timer interrupt may be pending while performing power-down. > + */ > + riscv_clock_event_stop(); > + > return 0; > } Should it not be the opposite? First stop the clock which clears the interrupt and then disable the irq? -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog