From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 904F530F7F0 for ; Mon, 27 Oct 2025 16:41:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761583267; cv=none; b=B6elq8Jo2Ou+7OajqpK4G5+LzZunDJ535fZVJbSCwezDkdyAn2igctECseh5la0Tedz+z3TfeiqXR2dQzxWtywooLosAI9ajLkc2gSHNK+jdwRqrYu14Xn/LBJRqqaoQ/8ZpIgTLSuMSG536JB1tj1WU2mzskyIkI2Eb7sH90kc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761583267; c=relaxed/simple; bh=YvO3EjSKrMULU4MU7n6apNKpcUJ205zLnvXrEAqn5rI=; h=Date:From:To:cc:Subject:In-Reply-To:Message-ID:References: MIME-Version:Content-Type; b=nkHnmsstbLwS/amBk04Cet2IdmXdZELnilcho3RqGSSxfJfrB50rBNs5SQ+2pkzup3i/JHe9aeJWRzL/byKbCnBrLGGbI/Wx9b+6Q2zPyynEOvqkhkyhwIHrVQCfNxRVQykvpjRSfoNaCI1X4GMC+/8sRmREYNs+ak7JEwvSxjk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jyIJ2kiA; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jyIJ2kiA" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4BC23C4CEFD; Mon, 27 Oct 2025 16:41:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761583267; bh=YvO3EjSKrMULU4MU7n6apNKpcUJ205zLnvXrEAqn5rI=; h=Date:From:To:cc:Subject:In-Reply-To:References:From; b=jyIJ2kiAogOLX8i/NYhD7/KSkrZa/7Dl/4JnqQCG0wbkW8JkOpJ0399YbBT+e5bgh sxKqSnX0EklHI/SURIyAu3FPx8xvl4T105n94+bglWtBaudmMGFyk5QEiFOtaSF8L2 zcO3TRHXiPQ+XoP2PKyI4Zt9hJqaDUfKNoEfpawoV/Dzd6Wx0saA5OWNPQiJIO9elU VoQZGb9THsu9D/uVQ35QVhoqk1dwlOTpmsLmhrMaU5TM3Ij3K2pBEgMPVzQegh+kpf x56bRGBxJozYgYTakX2KZwaK+NvFxxxbR6RlvAwhYVkD/bSneEHRXX84pxeYakQR4S 6v8GAudwoNIUQ== Date: Mon, 27 Oct 2025 10:41:01 -0600 (MDT) From: Paul Walmsley To: =?ISO-8859-15?Q?Christian_K=F6nig?= cc: Icenowy Zheng , Huang Rui , Matthew Auld , Matthew Brost , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Han Gao , Vivian Wang , Inochi Amaoto , Yao Zi Subject: Re: [PATCH v2] drm/ttm: add pgprot handling for RISC-V In-Reply-To: Message-ID: <5fed2297-4e51-6aa9-464a-6f8a2cf8fcc6@kernel.org> References: <20251020053523.731353-1-uwu@icenowy.me> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/mixed; BOUNDARY="8323329-798525650-1761583098=:20800" Content-ID: This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. --8323329-798525650-1761583098=:20800 Content-Type: text/plain; CHARSET=ISO-8859-15 Content-Transfer-Encoding: 8BIT Content-ID: On Mon, 27 Oct 2025, Christian König wrote: > On 10/20/25 07:35, Icenowy Zheng wrote: > > The RISC-V Svpbmt privileged extension provides support for overriding > > page memory coherency attributes, and, along with vendor extensions like > > Xtheadmae, supports pgprot_{writecombine,noncached} on RISC-V. > > > > Adapt the codepath that maps ttm_write_combined to pgprot_writecombine > > and ttm_noncached to pgprot_noncached to RISC-V, to allow proper page > > access attributes. [ ... ] > > diff --git a/drivers/gpu/drm/ttm/ttm_module.c b/drivers/gpu/drm/ttm/ttm_module.c > > index b3fffe7b5062a..aa137ead5cc59 100644 > > --- a/drivers/gpu/drm/ttm/ttm_module.c > > +++ b/drivers/gpu/drm/ttm/ttm_module.c > > @@ -74,7 +74,8 @@ pgprot_t ttm_prot_from_caching(enum ttm_caching caching, pgprot_t tmp) > > #endif /* CONFIG_UML */ > > #endif /* __i386__ || __x86_64__ */ > > #if defined(__ia64__) || defined(__arm__) || defined(__aarch64__) || \ > > - defined(__powerpc__) || defined(__mips__) || defined(__loongarch__) > > + defined(__powerpc__) || defined(__mips__) || defined(__loongarch__) || \ > > + defined(__riscv) > > Looks reasonable, but does that work on all RISC-V variants? >From an RISC-V architectural perspective, yes. Of course there might be a hardware bug in some given manufacturer's implementation, but then again, that could happen on the other architectures as well. - Paul --8323329-798525650-1761583098=:20800--