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([2a00:f41:909a:a11e:b2c0:1360:9a97:b2b8]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a685b935b5csm614209666b.206.2024.06.04.10.35.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 04 Jun 2024 10:35:07 -0700 (PDT) Message-ID: <5ff40fba-e45a-4a5c-b5a7-7ef5a799a008@linaro.org> Date: Tue, 4 Jun 2024 19:35:04 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] drm/msm/adreno: De-spaghettify the use of memory barriers To: Akhil P Oommen Cc: Rob Clark , Sean Paul , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , Rob Clark , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20240508-topic-adreno-v1-1-1babd05c119d@linaro.org> <20240514183849.6lpyplifero5u35r@hu-akhilpo-hyd.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20240514183849.6lpyplifero5u35r@hu-akhilpo-hyd.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 5/14/24 20:38, Akhil P Oommen wrote: > On Wed, May 08, 2024 at 07:46:31PM +0200, Konrad Dybcio wrote: >> Memory barriers help ensure instruction ordering, NOT time and order >> of actual write arrival at other observers (e.g. memory-mapped IP). >> On architectures employing weak memory ordering, the latter can be a >> giant pain point, and it has been as part of this driver. >> >> Moreover, the gpu_/gmu_ accessors already use non-relaxed versions of >> readl/writel, which include r/w (respectively) barriers. >> >> Replace the barriers with a readback that ensures the previous writes >> have exited the write buffer (as the CPU must flush the write to the >> register it's trying to read back) and subsequently remove the hack >> introduced in commit b77532803d11 ("drm/msm/a6xx: Poll for GBIF unhalt >> status in hw_init"). >> >> Fixes: b77532803d11 ("drm/msm/a6xx: Poll for GBIF unhalt status in hw_init") >> Signed-off-by: Konrad Dybcio >> --- >> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 5 ++--- >> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 14 ++++---------- >> 2 files changed, 6 insertions(+), 13 deletions(-) > > I prefer this version compared to the v2. A helper routine is > unnecessary here because: > 1. there are very few scenarios where we have to read back the same > register. > 2. we may accidently readback a write only register. Which would still trigger an address dependency on the CPU, no? > >> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >> index 0e3dfd4c2bc8..4135a53b55a7 100644 >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >> @@ -466,9 +466,8 @@ static int a6xx_rpmh_start(struct a6xx_gmu *gmu) >> int ret; >> u32 val; >> >> - gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1 << 1); >> - /* Wait for the register to finish posting */ >> - wmb(); >> + gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, BIT(1)); >> + gmu_read(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ); > > This is unnecessary because we are polling on a register on the same port below. But I think we > can replace "wmb()" above with "mb()" to avoid reordering between read > and write IO instructions. Ok on the dropping readback part + AFAIU from Will's response, we can drop the barrier as well > >> >> ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_RSCC_CONTROL_ACK, val, >> val & (1 << 1), 100, 10000); >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> index 973872ad0474..0acbc38b8e70 100644 >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> @@ -1713,22 +1713,16 @@ static int hw_init(struct msm_gpu *gpu) >> } >> >> /* Clear GBIF halt in case GX domain was not collapsed */ >> + gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); > > We need a full barrier here to avoid reordering. Also, lets add a > comment about why we are doing this odd looking sequence. > >> + gpu_read(gpu, REG_A6XX_GBIF_HALT); >> if (adreno_is_a619_holi(adreno_gpu)) { >> - gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); >> gpu_write(gpu, REG_A6XX_RBBM_GPR0_CNTL, 0); >> - /* Let's make extra sure that the GPU can access the memory.. */ >> - mb(); > > We need a full barrier here. > >> + gpu_read(gpu, REG_A6XX_RBBM_GPR0_CNTL); >> } else if (a6xx_has_gbif(adreno_gpu)) { >> - gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); >> gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0); >> - /* Let's make extra sure that the GPU can access the memory.. */ >> - mb(); > > We need a full barrier here. Not sure we do between REG_A6XX_GBIF_HALT & REG_A6XX_RBBM_(GBIF_HALT/GPR0_CNTL), but I suppose keeping the one after REG_A6XX_RBBM_(GBIF_HALT/GPR0_CNTL) makes sense to avoid the possibility of configuring the GPU before it can access DRAM.. > >> + gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT); >> } >> >> - /* Some GPUs are stubborn and take their sweet time to unhalt GBIF! */ >> - if (adreno_is_a7xx(adreno_gpu) && a6xx_has_gbif(adreno_gpu)) >> - spin_until(!gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK)); >> - > > Why is this removed? Because it was a hack in the first place and the enforcement of GBIF unhalt requests coming through before proceeding further removes the necessity to check this (unless there's some hw-mandated delay we should keep in mind, but kgsl doesn't have that and there doesn't seem to be any from testing on 8[456]50). Konrad