From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out30-113.freemail.mail.aliyun.com (out30-113.freemail.mail.aliyun.com [115.124.30.113]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB3B4269811 for ; Mon, 8 Dec 2025 02:33:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.113 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765161189; cv=none; b=qKmLSK6RBjFUyEs3HyRbXPG9bkQo1aKWuQ4k/Mnl08xHMGrXVTMuVRC2jGsC746JM/FUNfGNXCaJROPMYCMhelMHSRz92iIxVc/cWnWnciMNfW83rz1maesylvog/1Ngjto2WYb4y564whP8WEoBcW2u2s4CFKHN5NELYvWbo9k= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765161189; c=relaxed/simple; bh=moKz4GVRNv207Zrvanx1wM3yetaz/fdkn5XTair9WKI=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=ll76pG0LxJy0s2Y3WpmMKzCEbMhupGKbFQgDjFviBZm/TKvKQ4lIP/nRfplVqAR8n0zhj0qnAeKvCeYcuurVmqGHMld1oGuau5g0TQptRITYbUcOEzkOhaoUZ1Vzl5jKoq6AXzvsxyVJN2EHh6YMnzqerBRs1ase+wrrskoIQQo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=GnW/ymj+; arc=none smtp.client-ip=115.124.30.113 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="GnW/ymj+" DKIM-Signature:v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1765161183; h=Message-ID:Date:MIME-Version:Subject:To:From:Content-Type; bh=+m9wTg+ZYkNO109SezDDzdMKSU7d9+BVzHXwQxnLF5s=; b=GnW/ymj+lsmzQZNj7lLaJT7Syj11waeMUV7yqqruDLVbG7rqzAvhXazaKyo3qq+zrK8Roxe3ugR0fNttZT1PTGMebvGguwmbIZtRNAkUg1fyZbqYSSz+2zBycEpcl0socnEKZM4rUotLms+6lpX2QkSQ269xt4yACac/blrZ0/g= Received: from 30.246.178.18(mailfrom:xueshuai@linux.alibaba.com fp:SMTPD_---0WuF431u_1765161182 cluster:ay36) by smtp.aliyun-inc.com; Mon, 08 Dec 2025 10:33:02 +0800 Message-ID: <60060fca-b1e7-43d9-b1de-27bc9ec2f43f@linux.alibaba.com> Date: Mon, 8 Dec 2025 10:33:01 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH rc v2 1/4] iommu/arm-smmu-v3: Add ignored bits to fix STE update sequence To: Nicolin Chen , jgg@nvidia.com, will@kernel.org, robin.murphy@arm.com Cc: joro@8bytes.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, skolothumtho@nvidia.com, praan@google.com References: <0db5caabdcdd8aa170f4c196e94d54664cc87fd3.1765140287.git.nicolinc@nvidia.com> From: Shuai Xue In-Reply-To: <0db5caabdcdd8aa170f4c196e94d54664cc87fd3.1765140287.git.nicolinc@nvidia.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit 在 2025/12/8 04:49, Nicolin Chen 写道: > From: Jason Gunthorpe > > C_BAD_STE was observed when updating nested STE from an S1-bypass mode to > an S1DSS-bypass mode. As both modes enabled S2, the used bit is slightly > different than the normal S1-bypass and S1DSS-bypass modes. As a result, > fields like MEV and EATS in S2's used list marked the word1 as a critical > word that requested a STE.V=0. This breaks a hitless update. > > However, both MEV and EATS aren't critical in terms of STE update. One > controls the merge of the events and the other controls the ATS that is > managed by the driver at the same time via pci_enable_ats(). > > Add an arm_smmu_get_ste_ignored() to allow STE update algorithm to ignore > those fields, avoiding the STE update breakages. > > Note that this change is required by both MEV and EATS fields, which were > introduced in different kernel versions. So add this get_ignored() first. > The MEV and EATS will be added in arm_smmu_get_ste_ignored() separately. > > Fixes: 1e8be08d1c91 ("iommu/arm-smmu-v3: Support IOMMU_DOMAIN_NESTED") > Cc: stable@vger.kernel.org > Signed-off-by: Jason Gunthorpe > Signed-off-by: Nicolin Chen > --- Reviewed-by: Shuai Xue Thanks. Shuai