From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72208C7EE21 for ; Fri, 5 May 2023 02:21:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229907AbjEECUy (ORCPT ); Thu, 4 May 2023 22:20:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33736 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229524AbjEECUv (ORCPT ); Thu, 4 May 2023 22:20:51 -0400 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 49EF0AD3F; Thu, 4 May 2023 19:20:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1683253250; x=1714789250; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=3cB8FCltPb4XWCTQOTTNGU/NtPGFR9grO1Z1GyYNzXQ=; b=dffgtO/rUrlY4TUhEWWGvB3SIRa2Y81W7MFABgT8hEEL3lwmKlcDHTab WHagGDlMYmys5DroopGjEoZh4wlRV/F3ZLssoHk3So3HAAjgT/uEIem0o OYEvQJm4WIxJjd5qyBYYaNlp7K6sq05obsBrnv3Ou1Eg5RPZeTKJEgzTQ QtMVztXshcNlWQCKZJQq8+/Z2p7p2TqaMAf/kw3M1njxsHA1i/IVs4P/0 T+wX0d4xg4tXXMD3Wt3amKnDUgP6NdJQaEJkLyz+grusqjrVAZyhMkgZ9 ZNvNqBU1ePg+VG+ikfbVRTLF163phAg7yi1Jx4Fcy5iz/2g/Ct2QdxYja A==; X-IronPort-AV: E=McAfee;i="6600,9927,10700"; a="333526403" X-IronPort-AV: E=Sophos;i="5.99,250,1677571200"; d="scan'208";a="333526403" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 May 2023 19:18:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10700"; a="674816299" X-IronPort-AV: E=Sophos;i="5.99,250,1677571200"; d="scan'208";a="674816299" Received: from yuzhongq-mobl.ccr.corp.intel.com (HELO [10.255.29.220]) ([10.255.29.220]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 May 2023 19:18:34 -0700 Message-ID: <600c42ab-44a8-d2cd-57c4-d423a8516d0a@linux.intel.com> Date: Fri, 5 May 2023 10:18:32 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.10.1 Subject: Re: [PATCH v2 11/21] KVM:VMX: Introduce CET VMCS fields and control bits To: Yang Weijiang , seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, john.allen@amd.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: rick.p.edgecombe@intel.com, Zhang Yi Z References: <20230421134615.62539-1-weijiang.yang@intel.com> <20230421134615.62539-12-weijiang.yang@intel.com> From: Binbin Wu In-Reply-To: <20230421134615.62539-12-weijiang.yang@intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 4/21/2023 9:46 PM, Yang Weijiang wrote: > CET (Control-flow Enforcement Technology) is a CPU feature used to prevent > Return/Jump-Oriented Programming (ROP/JOP) attacks. CET introduces a new > exception type, Control Protection (#CP), and two sub-features(SHSTK,IBT) > to defend against ROP/JOP style control-flow subversion attacks. > > Shadow Stack (SHSTK): > A shadow stack is a second stack used exclusively for control transfer > operations. The shadow stack is separate from the data/normal stack and > can be enabled individually in user and kernel mode. When shadow stacks > are enabled, CALL pushes the return address on both the data and shadow > stack. RET pops the return address from both stacks and compares them. > If the return addresses from the two stacks do not match, the processor > signals a #CP. > > Indirect Branch Tracking (IBT): > IBT adds a new instrution, ENDBRANCH, that is used to mark valid target /s/instrution/instruction > addresses of indirect branches (CALL, JMP, ENCLU[EEXIT], etc...). If an > indirect branch is executed and the next instruction is _not_ an > ENDBRANCH, the processor signals a #CP. > > Several new CET MSRs are defined to support CET: > MSR_IA32_{U,S}_CET: Controls the CET settings for user mode and kernel > mode respectively. > > MSR_IA32_PL{0,1,2,3}_SSP: Stores shadow stack pointers for CPL-0,1,2,3 > protection respectively. > > MSR_IA32_INT_SSP_TAB: Stores base address of shadow stack pointer table. According to the name of the MSR, it is interrupt related, right? It's better to describe the MSR more precisely. > > Two XSAVES state bits are introduced for CET: > IA32_XSS:[bit 11]: Control saving/restoring user mode CET states > IA32_XSS:[bit 12]: Control saving/restoring kernel mode CET states. > > Six VMCS fields are introduced for CET: > {HOST,GUEST}_S_CET: Stores CET settings for kernel mode. > {HOST,GUEST}_SSP: Stores shadow stack pointer of current active task/thread. > {HOST,GUEST}_INTR_SSP_TABLE: Stores base address of shadow stack pointer table. ditto > > If VM_EXIT_LOAD_HOST_CET_STATE = 1, the host CET states are restored from > the following VMCS fields at VM-Exit: > HOST_S_CET > HOST_SSP > HOST_INTR_SSP_TABLE > > If VM_ENTRY_LOAD_GUEST_CET_STATE = 1, the guest CET states are loaded from > the following VMCS fields at VM-Entry: > GUEST_S_CET > GUEST_SSP > GUEST_INTR_SSP_TABLE > > Co-developed-by: Zhang Yi Z > Signed-off-by: Zhang Yi Z > Signed-off-by: Yang Weijiang > --- > arch/x86/include/asm/vmx.h | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h > index 498dc600bd5c..fe2aff27df8c 100644 > --- a/arch/x86/include/asm/vmx.h > +++ b/arch/x86/include/asm/vmx.h > @@ -102,6 +102,7 @@ > #define VM_EXIT_CLEAR_BNDCFGS 0x00800000 > #define VM_EXIT_PT_CONCEAL_PIP 0x01000000 > #define VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000 > +#define VM_EXIT_LOAD_CET_STATE 0x10000000 > > #define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR 0x00036dff > > @@ -115,6 +116,7 @@ > #define VM_ENTRY_LOAD_BNDCFGS 0x00010000 > #define VM_ENTRY_PT_CONCEAL_PIP 0x00020000 > #define VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000 > +#define VM_ENTRY_LOAD_CET_STATE 0x00100000 > > #define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR 0x000011ff > > @@ -343,6 +345,9 @@ enum vmcs_field { > GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822, > GUEST_SYSENTER_ESP = 0x00006824, > GUEST_SYSENTER_EIP = 0x00006826, > + GUEST_S_CET = 0x00006828, > + GUEST_SSP = 0x0000682a, > + GUEST_INTR_SSP_TABLE = 0x0000682c, > HOST_CR0 = 0x00006c00, > HOST_CR3 = 0x00006c02, > HOST_CR4 = 0x00006c04, > @@ -355,6 +360,9 @@ enum vmcs_field { > HOST_IA32_SYSENTER_EIP = 0x00006c12, > HOST_RSP = 0x00006c14, > HOST_RIP = 0x00006c16, > + HOST_S_CET = 0x00006c18, > + HOST_SSP = 0x00006c1a, > + HOST_INTR_SSP_TABLE = 0x00006c1c > }; > > /*