From: Andrew Lunn <andrew@lunn.ch>
To: Maxime Chevallier <maxime.chevallier@bootlin.com>
Cc: "Russell King (Oracle)" <linux@armlinux.org.uk>,
"Kory Maincent" <kory.maincent@bootlin.com>,
"Oleksij Rempel" <o.rempel@pengutronix.de>,
davem@davemloft.net, netdev@vger.kernel.org,
linux-kernel@vger.kernel.org, thomas.petazzoni@bootlin.com,
"Jakub Kicinski" <kuba@kernel.org>,
"Eric Dumazet" <edumazet@google.com>,
"Paolo Abeni" <pabeni@redhat.com>,
linux-arm-kernel@lists.infradead.org,
"Christophe Leroy" <christophe.leroy@csgroup.eu>,
"Herve Codina" <herve.codina@bootlin.com>,
"Florian Fainelli" <f.fainelli@gmail.com>,
"Heiner Kallweit" <hkallweit1@gmail.com>,
"Vladimir Oltean" <vladimir.oltean@nxp.com>,
"Marek Behún" <kabel@kernel.org>,
"Nicolò Veronese" <nicveronese@gmail.com>,
"Simon Horman" <horms@kernel.org>,
mwojtas@chromium.org, "Antoine Tenart" <atenart@kernel.org>
Subject: Re: [PATCH net-next RFC 0/5] net: phy: Introduce a port representation
Date: Tue, 7 Jan 2025 17:22:51 +0100 [thread overview]
Message-ID: <601067b3-2f8a-4080-9141-84a069db276e@lunn.ch> (raw)
In-Reply-To: <20250107171507.06908d71@fedora.home>
> I have however seen devices that have a 1G PHY connected to a RJ45
> port with 2 lanes only, thus limiting the max achievable speed to 100M.
> Here, we would explicietly describe the port has having 2 lanes.
Some PHYs would handle this via downshift, detecting that some pairs
are broken, and then dropping down to 100M on their own. So it is not
always necessary to have a board property, at least not for data.
I've no idea how this affects power transfer. Can the link partners
detect which pairs are actually wired?
Andrew
next prev parent reply other threads:[~2025-01-07 16:22 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-20 20:14 Maxime Chevallier
2024-12-20 20:15 ` [PATCH net-next RFC 1/5] net: ethtool: common: Make BaseT a 4-lanes mode Maxime Chevallier
2024-12-20 20:15 ` [PATCH net-next RFC 2/5] net: ethtool: Introduce ETHTOOL_LINK_MEDIUM_* values Maxime Chevallier
2024-12-20 20:15 ` [PATCH net-next RFC 3/5] net: ethtool: Export the link_mode_params definitions Maxime Chevallier
2024-12-20 20:15 ` [PATCH net-next RFC 4/5] net: phy: Introduce PHY ports representation Maxime Chevallier
2024-12-20 20:15 ` [PATCH net-next RFC 5/5] net: phy: dp83822: Add support for phy_port representation Maxime Chevallier
2024-12-22 15:59 ` [PATCH net-next RFC 0/5] net: phy: Introduce a port representation Oleksij Rempel
2024-12-22 18:54 ` Oleksij Rempel
2025-01-02 10:48 ` Russell King (Oracle)
2025-01-02 17:03 ` Oleksij Rempel
2025-01-07 13:26 ` Kory Maincent
2025-01-07 14:02 ` Oleksij Rempel
2025-01-07 14:43 ` Kory Maincent
2025-01-07 14:53 ` Oleksij Rempel
2025-01-07 15:14 ` Russell King (Oracle)
2025-01-07 15:54 ` Oleksij Rempel
2025-01-07 15:12 ` Russell King (Oracle)
2025-01-07 16:13 ` Andrew Lunn
2025-01-07 16:15 ` Maxime Chevallier
2025-01-07 16:22 ` Andrew Lunn [this message]
2025-01-07 16:41 ` Oleksij Rempel
2025-01-07 16:49 ` Oleksij Rempel
2025-01-08 7:25 ` Maxime Chevallier
2025-01-08 8:12 ` Oleksij Rempel
2025-01-04 22:23 ` Kory Maincent
2025-01-06 18:17 ` Oleksij Rempel
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