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[130.180.211.218]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-39c301a6a60sm10022277f8f.29.2025.04.06.13.33.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 06 Apr 2025 13:33:36 -0700 (PDT) Message-ID: <60132403-d849-47a7-a11c-e829ffefc7a9@linaro.org> Date: Sun, 6 Apr 2025 22:33:35 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/2] dt-bindings: watchdog: Add NXP Software Watchdog Timer To: Ghennadi Procopciuc , wim@linux-watchdog.org Cc: linux@roeck-us.net, linux-watchdog@vger.kernel.org, linux-kernel@vger.kernel.org, S32@nxp.com, ghennadi.procopciuc@nxp.com, thomas.fossati@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, Vincent Guittot References: <20250402154942.3645283-1-daniel.lezcano@linaro.org> <20250402154942.3645283-2-daniel.lezcano@linaro.org> <64b6d599-fe67-586a-e4b0-73d9b73499de@oss.nxp.com> <93d83df2-d3bc-e32d-70a6-158571504275@oss.nxp.com> Content-Language: en-US From: Daniel Lezcano In-Reply-To: <93d83df2-d3bc-e32d-70a6-158571504275@oss.nxp.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 04/04/2025 08:35, Ghennadi Procopciuc wrote: > On 4/3/2025 6:10 PM, Daniel Lezcano wrote: >> On 03/04/2025 08:19, Ghennadi Procopciuc wrote: >>> On 4/2/2025 6:49 PM, Daniel Lezcano wrote: >>> [ ... ] >>>> +examples: >>>> +  - | >>>> +    watchdog@0x40100000 { >>>> +        compatible = "nxp,s32g2-swt"; >>>> +        reg = <0x40100000 0x1000>; >>>> +        clocks = <&clks 0x3a>; >>>> +        timeout-sec = <10>; >>>> +    }; >>> >>> The S32G reference manual specifies two clocks for the SWT module: one >>> for the registers and another for the counter itself. Shouldn't both >>> clocks be represented in the bindings? >> >> AFAICS, there are two clocks as described in the documentation for the >> s32g2 page 846, section 23.7.3.3 SWT clocking. > > This diagram illustrates the module clocks and their connections to the > S32GS system clocks. From the module's perspective, there are three > clocks: MODULE_CLOCK, REG_INTF, and COUNTER_CLOCK. Specifically, on > S32G2 SoCs, the first two are connected to XBAR_DIV3_CLK, while the > counter clock is linked to FIRC_CLK. Based on my understanding of the > device tree, this configuration should be listed as follows: > > clocks = <&clks XBAR_DIV3_CLK>, <&clks XBAR_DIV3_CLK>, <&clks FIRC_CLK>; > clock-names = "module", "reg", "counter"; > > Configuring it this way allows flexibility to reuse the same clocking > scheme for other SoCs where the integration is performed differently. It > is possible that the 'module' and 'reg' clocks could be linked to two > distinct system clocks. That is something we can handle when the other SoC will be in the process of being upstream, no ? I don't see how that can help with the current hardware we are describing. What is the benefit ? I would prefer to stick to what is needed today >> The module and the register clock are fed by the XBAR_DIV3_CLK which is >> an system clock always-on. > > XBAR_DIV3_CLK is not an always-on clock, meaning it is not available > during suspend, if that is what you mean by always-on. The SIRC can be > considered the only always-on clock on this device. > >> >> The counter is fed by the FIRC_CLK which described as "FIRC_CLK is the >> default clock for the entire system at power-up." >> >> From my understanding, we should not describe the XBAR_DIV3_CLK as it is >> a system clock. >> >> And the FIRC_CLK is only there to get the clock rate in the driver. >> > -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog