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Thu, 18 Jun 2026 13:52:06 +0200 Message-ID: <604a73b122bd5fb7b35fe5bfeb0352bd9fd99046.camel@pengutronix.de> Subject: Re: [PATCH 2/9] drm/rockchip: vop2: Reset AXI and DCLK to improve robustness From: Philipp Zabel To: Cristian Ciocaltea , Sandy Huang , Heiko =?ISO-8859-1?Q?St=FCbner?= , Andy Yan , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli Cc: kernel@collabora.com, Andy Yan , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Date: Thu, 18 Jun 2026 13:52:05 +0200 In-Reply-To: <302d42b0-108e-4936-bc34-49b9194985f1@collabora.com> References: <20260617-dw-hdmi-qp-yuv-v1-0-a665cfd06d7d@collabora.com> <20260617-dw-hdmi-qp-yuv-v1-2-a665cfd06d7d@collabora.com> <7c79f233c863654b0266de4b5ec5a8c72bb17715.camel@pengutronix.de> <302d42b0-108e-4936-bc34-49b9194985f1@collabora.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2-0+deb13u1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Do, 2026-06-18 at 14:46 +0300, Cristian Ciocaltea wrote: > On 6/18/26 12:39 PM, Philipp Zabel wrote: > > On Mi, 2026-06-17 at 21:51 +0300, Cristian Ciocaltea wrote: > > > Assert the AXI reset in the CRTC disable path, and the VP DCLK reset = in > > > the enable path. > > >=20 > > > These resets are intended to leave the hardware in a clean state for = the > > > next use, helping recover from exceptions such as IOMMU page faults, = as > > > well as to prevent random display output glitches, such as a blank > > > image, observed when switching modes that also change the color forma= t, > > > e.g. from RGB to YUV420 and vice versa. > > >=20 > > > For now this seems to affect only the RK3588, hence the resets are > > > optional and will be provided in the device tree for this SoC only. > > >=20 > > > Co-developed-by: Andy Yan > > > Signed-off-by: Andy Yan > > > Signed-off-by: Cristian Ciocaltea > > > --- > > > drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 35 ++++++++++++++++++= ++++++++++ > > > drivers/gpu/drm/rockchip/rockchip_drm_vop2.h | 4 ++++ > > > 2 files changed, 39 insertions(+) > > >=20 > > > diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/g= pu/drm/rockchip/rockchip_drm_vop2.c > > > index 4cce3e336f5b..2833fb49ad81 100644 > > > --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c > > > +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c > > > @@ -17,6 +17,7 @@ > > > #include > > > #include > > > #include > > > +#include > > > #include > > > =20 > > > #include > > > @@ -860,6 +861,26 @@ static int vop2_core_clks_prepare_enable(struct = vop2 *vop2) > > > return ret; > > > } > > > =20 > > > +static void vop2_clk_reset(struct vop2 *vop2, struct reset_control *= rstc) > >=20 > > The _clk part of the function name is misleading ... >=20 > Ack. =20 >=20 > We need to make this clearly distinct from another similarly named functi= on, > vop2_crtc_reset(), hence I'd propose: >=20 > - vop2_reset_assert_deassert() > - vop2_reset_cycle() > - vop2_do_reset() >=20 > Any preference / alternative suggestions? Or vop2_reset_control_reset(). The three above are equally fine. regards Philipp