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Fri, 07 Aug 2026 16:19:27 +0200 (CEST) Message-ID: <605f96b2-709c-49f6-9446-49ed3bff7d96@collabora.com> Date: Fri, 7 Aug 2026 17:19:27 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 02/10] phy: rockchip: samsung-hdptx: Prevent divide-by-zero when computing clk rate To: Manivannan Sadhasivam Cc: Vinod Koul , Neil Armstrong , Heiko Stuebner , Algea Cao , Dmitry Baryshkov , kernel@collabora.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Sashiko , Diederik de Haas , Dmitry Baryshkov , Andy Yan References: <20260723-hdptx-clk-fixes-v5-0-8e786067865f@collabora.com> <20260723-hdptx-clk-fixes-v5-2-8e786067865f@collabora.com> Content-Language: en-US From: Cristian Ciocaltea In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi Mani, On 8/7/26 3:56 PM, Manivannan Sadhasivam wrote: > On Thu, Jul 23, 2026 at 10:41:45PM +0300, Cristian Ciocaltea wrote: >> Calculating 'sdm' fraction in rk_hdptx_phy_clk_calc_rate_from_pll_cfg() >> could trigger a divide-by-zero, as it uses div_u64() with a denominator >> read directly from hardware: the values ropll_hw.sdm_deno, >> ropll_hw.sdc_deno, ropll_hw.sdc_n, and ropll_hw.sdc_num are populated >> from PLL registers which, in theory, could be left by the bootloader >> uninitialized/misconfigured. >> >> Provide the necessary sanitization to avoid trusting the hardware state. >> >> Reported-by: Sashiko >> Closes: https://sashiko.dev/#/patchset/20260611-hdptx-clk-fixes-v3-0-67b1b0c00e16@collabora.com?part=1 >> Fixes: 3481fc04d969 ("phy: rockchip: samsung-hdptx: Compute clk rate from PLL config") >> Tested-by: Diederik de Haas # NanoPC-T6 LTS >> Reviewed-by: Dmitry Baryshkov >> Reviewed-by: Andy Yan >> Signed-off-by: Cristian Ciocaltea >> --- >> drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 11 ++++++++--- >> 1 file changed, 8 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c >> index 710603afff86..44e99343f249 100644 >> --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c >> +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c >> @@ -2270,10 +2270,15 @@ static u64 rk_hdptx_phy_clk_calc_rate_from_pll_cfg(struct rk_hdptx_phy *hdptx) >> >> fout = PLL_REF_CLK * ropll_hw.pms_mdiv; >> if (ropll_hw.sdm_en) { >> + val = 16U * ropll_hw.sdm_deno * >> + (ropll_hw.sdc_deno * ropll_hw.sdc_n - ropll_hw.sdc_num); >> + if (!val) { >> + dev_dbg(hdptx->dev, "Invalid ROPLL hw state: deno == 0\n"); > > If the hardware state is invalid, why can't this be a hard failure? This is an internal helper called from the .recalc_rate clk_op, which tries to compute the current rate by reading back the hardware state. Since .recalc_rate returns unsigned long, we cannot propagate errors to the caller. However, per the clk_ops documentation, the driver is expected to return 0 if it cannot figure out the rate. Moreover, this condition isn't really fatal, as it only means the PLL configuration currently stored in hardware can't be translated into a rate. The next .set_rate should program a valid configuration and help with the recovery. Thanks for reviewing! Regards, Cristian