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Mon, 20 Jan 2025 10:58:08 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 50KAw7mg010050 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 20 Jan 2025 10:58:07 GMT Received: from [10.217.217.81] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 20 Jan 2025 02:58:03 -0800 Message-ID: <608afa23-ca4e-48dd-b929-4466560a7e61@quicinc.com> Date: Mon, 20 Jan 2025 16:27:59 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] arm64: dts: qcom: Add cpu scaling clock node To: Dmitry Baryshkov CC: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ajit Pandey , Imran Shaik , "Jagadeesh Kona" , , , , References: <20241108-qcs615-mm-dt-nodes-v1-0-b2669cac0624@quicinc.com> <20241108-qcs615-mm-dt-nodes-v1-2-b2669cac0624@quicinc.com> <71635b71-71e4-4c17-add1-bf41ce770632@quicinc.com> <97f5f5b1-b4f9-4d0d-88fb-4c7a0f1c26ac@quicinc.com> Content-Language: en-US From: Taniya Das In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: IjIjC_4c4SZLBXqYN2FkF6KAWVZs2YGP X-Proofpoint-ORIG-GUID: IjIjC_4c4SZLBXqYN2FkF6KAWVZs2YGP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-20_02,2025-01-20_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 suspectscore=0 bulkscore=0 malwarescore=0 mlxscore=0 clxscore=1015 mlxlogscore=949 lowpriorityscore=0 impostorscore=0 spamscore=0 priorityscore=1501 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501200091 On 1/20/2025 4:06 PM, Dmitry Baryshkov wrote: > On Mon, 20 Jan 2025 at 12:34, Taniya Das wrote: >> >> >> >> On 1/20/2025 2:16 PM, Dmitry Baryshkov wrote: >>>>> This doesn't follow the bindings, does it? >>>> I will add and re-use the closest target compatible. >>>> >>>>>> + reg = <0 0x18323000 0 0x1400>, >>>>>> + <0 0x18325800 0 0x1400>; >>>>>> + reg-names = "freq-domain0", "freq-domain1"; >>>>>> + >>>>>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; >>>>>> + clock-names = "xo", "alternate"; >>>>> Are the DCVSH interrupts? >>>>> >>>> This target does not have DCVSH interrupts directly connected to the >>>> CPUFREQ-HW. >>> So, does it require a separate LMH driver, like the one used for sdm845? >> >> I will check how it is handled on QCS615 as it is closer to SC7180 and I >> didn't see any LMH handling there as well. > > At least sm6150-thermal.dtsi declares two LMH blocks. QCS615 also has 2 LMH blocks, but the handling of interrupts will be done from the LMH driver, integration with CPUFREQ-HW driver is still under evaluation. -- Thanks & Regards, Taniya Das.