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([2a00:11b1:1012:4c5c:60c0:dbec:5b5e:a393]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42012a025dbsm166085975e9.23.2024.05.16.03.29.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 16 May 2024 03:29:09 -0700 (PDT) Date: Thu, 16 May 2024 12:29:08 +0200 From: Andrew Jones To: Conor Dooley CC: Conor Dooley , linux-riscv@lists.infradead.org, xiao.w.wang@intel.com, pulehui@huawei.com, Charlie Jenkins , Paul Walmsley , Palmer Dabbelt , linux-kernel@vger.kernel.org Subject: =?US-ASCII?Q?Re=3A_=5BPATCH_v1=5D_RISC-V=3A_separate_Zbb_optimisatio?= =?US-ASCII?Q?ns_requiring_and_not_requiring_toolchain_support?= In-Reply-To: <20240516-speller-target-d453ad060486@wendy> References: <20240515-hedging-passage-44fd394ab1be@spud> <20240516-7ff4001c9f2edd2a61775244@orel> <20240516-speller-target-d453ad060486@wendy> Message-ID: <60EFC387-B19B-46A6-AD1B-D6DAC8108836@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On May 16, 2024 10:59:44 AM GMT+02:00, Conor Dooley wrote: >On Thu, May 16, 2024 at 09:59:44AM +0200, Andrew Jones wrote: >> On Wed, May 15, 2024 at 04:27:40PM GMT, Conor Dooley wrote: >>=20 >> So the new hidden config is a shorthand for >>=20 >> #if defined(CONFIG_RISCV_ISA_ZBB) && \ >> defined(CONFIG_TOOLCHAIN_HAS_ZBB) && \ >> defined(CONFIG_RISCV_ALTERNATIVE) >>=20 >> which is reasonable to add, since that's a mouthful, but I'm not sure t= he >> name, RISCV_ISA_ZBB_ALT, does a good job conveying all that=2E >>=20 >> If we instead just dropped the 'depends on TOOLCHAIN_HAS_ZBB' from >> config RISCV_ISA_ZBB (keeping the 'depends on RISCV_ALTERNATIVE', >> since nobody is really complaining about that), then we could change >> this to >>=20 >> #if defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB) > >Yeah, I think this is a cleaner solution=2E > >> > asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0, >> > RISCV_ISA_EXT_ZBB, 1) >> > : : : : legacy); >> > diff --git a/arch/riscv/include/asm/bitops=2Eh b/arch/riscv/include/a= sm/bitops=2Eh >> > index 880606b0469a=2E=2E3ed810a6123d 100644 >> > --- a/arch/riscv/include/asm/bitops=2Eh >> > +++ b/arch/riscv/include/asm/bitops=2Eh >> > @@ -15,7 +15,7 @@ >> > #include >> > #include >> > =20 >> > -#if !defined(CONFIG_RISCV_ISA_ZBB) || defined(NO_ALTERNATIVE) >> > +#if !defined(CONFIG_RISCV_ISA_ZBB_ALT) || defined(NO_ALTERNATIVE) >>=20 >> nit: It's sufficient to check !defined(CONFIG_RISCV_ISA_ZBB), so no nee= d >> for this change or its #endif comment change below=2E > >Are you sure? I did test leaving this as-was and it broke the build for >llvm-14=2E Oops, sorry=2E I didn't look at the full context=2E You were right=2E Thanks, drew > >Cheers, >Conor=2E