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Tue, 2 Sep 2025 07:47:48 +0000 Message-ID: <6113c4e9-9141-49bf-9672-0203c5cdbf88@intel.com> Date: Tue, 2 Sep 2025 10:47:42 +0300 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] mmc: sdhci-pci-gli: GL9767: Fix initializing the UHS-II interface during a power-on To: Ben Chuang CC: , , , , , , , References: <20250901094224.3920-1-benchuanggli@gmail.com> <18915c80-84c3-4a61-a5d2-d40387ec4eb7@intel.com> Content-Language: en-US From: Adrian Hunter Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-ClientProxiedBy: DUZPR01CA0036.eurprd01.prod.exchangelabs.com (2603:10a6:10:468::14) To DS0PR11MB7215.namprd11.prod.outlook.com (2603:10b6:8:13a::13) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: IA1PR11MB7198:EE_|MN6PR11MB8194:EE_ X-MS-Office365-Filtering-Correlation-Id: 476b4425-44de-4d41-6ece-08dde9f50238 X-LD-Processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|376014|7053199007; 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>>>> } >>>> >>>> +static void sdhci_gl9767_uhs2_phy_reset_assert(struct sdhci_host *host) >>>> +{ >>>> + struct sdhci_pci_slot *slot = sdhci_priv(host); >>>> + struct pci_dev *pdev = slot->chip->pdev; >>>> + u32 value; >>>> + >>>> + gl9767_vhs_write(pdev); >>>> + pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, &value); >>>> + value |= PCIE_GLI_9767_UHS2_CTL2_FORCE_PHY_RESETN; >>>> + pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value); >>>> + value &= ~PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE; >>>> + pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value); >>>> + gl9767_vhs_read(pdev); >>>> +} >>>> + >>>> +static void sdhci_gl9767_uhs2_phy_reset_deassert(struct sdhci_host *host) >>>> +{ >>>> + struct sdhci_pci_slot *slot = sdhci_priv(host); >>>> + struct pci_dev *pdev = slot->chip->pdev; >>>> + u32 value; >>>> + >>>> + gl9767_vhs_write(pdev); >>>> + pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, &value); >>>> + value |= PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE; >>> >>> Maybe add a small comment about PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE >>> and PCIE_GLI_9767_UHS2_CTL2_FORCE_PHY_RESETN being updated separately. >>> >>>> + pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value); >>>> + value &= ~PCIE_GLI_9767_UHS2_CTL2_FORCE_PHY_RESETN; >>>> + pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value); >>>> + gl9767_vhs_read(pdev); >>>> +} >>> >>> sdhci_gl9767_uhs2_phy_reset_assert() and sdhci_gl9767_uhs2_phy_reset_deassert() >>> are fairly similar. Maybe consider: >>> >>> static void sdhci_gl9767_uhs2_phy_reset(struct sdhci_host *host, bool assert) >>> { >>> struct sdhci_pci_slot *slot = sdhci_priv(host); >>> struct pci_dev *pdev = slot->chip->pdev; >>> u32 value, set, clr; >>> >>> if (assert) { >>> set = PCIE_GLI_9767_UHS2_CTL2_FORCE_PHY_RESETN; >>> clr = PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE; >>> } else { >>> set = PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE; >>> clr = PCIE_GLI_9767_UHS2_CTL2_FORCE_PHY_RESETN; >>> } >>> >>> gl9767_vhs_write(pdev); >>> pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, &value); >>> value |= set; >>> pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value); >>> value &= ~clr; >>> pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value); >>> gl9767_vhs_read(pdev); >>> } >>> >> >> OK, I will update it. Thank you. >> >>> >>>> + >>>> +static void __gl9767_uhs2_set_power(struct sdhci_host *host, unsigned char mode, unsigned short vdd) >>>> +{ >>>> + u8 pwr = 0; >>>> + >>>> + if (mode != MMC_POWER_OFF) { >>>> + pwr = sdhci_get_vdd_value(vdd); >>>> + if (!pwr) >>>> + WARN(1, "%s: Invalid vdd %#x\n", >>>> + mmc_hostname(host->mmc), vdd); >>>> + pwr |= SDHCI_VDD2_POWER_180; >>>> + } >>>> + >>>> + if (host->pwr == pwr) >>>> + return; >>>> + >>>> + host->pwr = pwr; >>>> + >>>> + if (pwr == 0) { >>>> + sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); >>>> + } else { >>>> + sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); >>>> + >>>> + pwr |= SDHCI_POWER_ON; >>>> + sdhci_writeb(host, pwr & 0xf, SDHCI_POWER_CONTROL); >>>> + mdelay(5); >>> >>> Can be mmc_delay(5) >>> >>>> + >>>> + sdhci_gl9767_uhs2_phy_reset_assert(host); >>>> + pwr |= SDHCI_VDD2_POWER_ON; >>>> + sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); >>>> + mdelay(5); >>> >>> Can be mmc_delay(5) >> >> I may not modify it now. >> mmc_delay() is in "drivers/mmc/core/core.h". >> If sdhci-pci-gli.c only includes "../core/core.h", the compiler will >> report some errors. > > Ah, just add another headersand it will build. > > --- a/drivers/mmc/host/sdhci-pci-gli.c > +++ b/drivers/mmc/host/sdhci-pci-gli.c > @@ -14,6 +14,8 @@ > #include > #include > #include > +#include > +#include "../core/core.h" > #include "sdhci.h" > #include "sdhci-cqhci.h" > #include "sdhci-pci.h" > @@ -968,10 +970,10 @@ static void gl9755_set_power(struct sdhci_host > *host, unsigned char mode, > > sdhci_writeb(host, pwr & 0xf, SDHCI_POWER_CONTROL); > /* wait stable */ > - mdelay(5); > + mmc_delay(5); > sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); > /* wait stable */ > - mdelay(5); > + mmc_delay(5); > sdhci_gli_overcurrent_event_enable(host, true); > } It seems mmc_delay() is for core mmc code only, not host drivers. But the issue with mdelay is that it does not sleep. Other options are msleep() or usleep_range().