From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934144AbdAJPAi (ORCPT ); Tue, 10 Jan 2017 10:00:38 -0500 Received: from mout.kundenserver.de ([217.72.192.74]:52322 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1763798AbdAJNnJ (ORCPT ); Tue, 10 Jan 2017 08:43:09 -0500 From: Arnd Bergmann To: Robin Murphy Cc: Nikita Yushchenko , Will Deacon , linux-arm-kernel@lists.infradead.org, Catalin Marinas , linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Simon Horman , Bjorn Helgaas , artemi.ivanov@cogentembedded.com, fkan@apm.com, Christoph Hellwig Subject: Re: [PATCH v2] arm64: do not set dma masks that device connection can't handle Date: Tue, 10 Jan 2017 14:42:23 +0100 Message-ID: <6116278.nQQUSuo3l4@wuerfel> User-Agent: KMail/5.1.3 (Linux/4.4.0-34-generic; KDE/5.18.0; x86_64; ; ) In-Reply-To: <11daacde-5399-039f-80a3-01d7bd13e9e8@arm.com> References: <1483947002-16410-1-git-send-email-nikita.yoush@cogentembedded.com> <07253eaa-5729-0f15-42b6-e8403f1f0412@cogentembedded.com> <11daacde-5399-039f-80a3-01d7bd13e9e8@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-Provags-ID: V03:K0:dCkLb917hk1UOtQ5MpG0sOV9HT2BP5DTLvHsgqQRnhf088cF/IX 2GusXdYQ9K2LdgDo7g3SbLAzaHhssebv9w5Xegxq68am0O03gvlF7ScC3nyNe26kTOWv1Uo AmxlMn5Sf9W3PCo3iQ90acspcmiIMcM7ZbD2CTmPvP85Kzq6wJptsL83eKBcveJY++uLqdY VhtW2A1ainoNjVO9JuugQ== X-UI-Out-Filterresults: notjunk:1;V01:K0:pncn0Cm6Bws=:PlA6mT6emk4ysaY2QTN0MX hup72QkiHIKaK5U5U2nSgYj97mWSF4C2iGI/Rhg8vYfH+ysPu+fJwo5i86GSvAA+SwcAvkC2/ PZ2YKvW4C1L1+ZKFF13sj+lfzeCKRB3AD2xbccaF/Q3+a8b/HHcI0RyTGT8aAXC41M9WuUaou byFdnXK6aK0Y6extETVT1UzF8B8yd7u8ZZNAxdmifvt/zXvZ7UCtyPOrJrECKqhMkuo90/kaD eXcIueosTI6MMLr81tBl1qSAY+5TxPwoaju941kTighffDz9hn0DiDKzI2QvAsaKrbIfPKMhj kzti/DDQtWx5ccBAWry6PKdTTNCorHOy5jyUZlqYsb3/EUCD3JrjYTl8EpEoaRUFDF2OS4PMr R+X70dQOC9lFCH0iNZMpSR1WcwhrIvEBKlzOp+YH34j1iFOyoQ7ldaqjgFauuH6vxgk/SVO9X 1UhdWm/ur60OJNUwV473zonW3del0Rzc9z3ioFRt39aKX+oR5h/V9N7gfEpjnR3IspfyJERBl WcpeFlMpgrDDi3d7nx0B/Oj1IkNXZFngY58RhFfeQ9DA6nZZ9kCybw8dISbM9G4p8/ayp2RII Thd/wNz4C6RR7ZvDEhIbT3eJEOHHwLgQ3oy6lJeNwxZUUhmw8cS+dpDV62wx0Mo7/6KbJgz7U dTxST65ouogZsU26OD99IGea/lqlqQIuzMrlwVvrDd2GXAwZLWFi+8s9Yyor0QyD7nb8g3e+u c6l+doPCIzE+IvKM Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tuesday, January 10, 2017 1:25:12 PM CET Robin Murphy wrote: > On 10/01/17 12:47, Nikita Yushchenko wrote: > >> The point here is that an IOMMU doesn't solve your issue, and the > >> IOMMU-backed DMA ops need the same treatment. In light of that, it really > >> feels to me like the DMA masks should be restricted in of_dma_configure > >> so that the parent mask is taken into account there, rather than hook > >> into each set of DMA ops to intercept set_dma_mask. We'd still need to > >> do something to stop dma_set_mask widening the mask if it was restricted > >> by of_dma_configure, but I think Robin (cc'd) was playing with that. > > > > What issue "IOMMU doesn't solve"? > > > > Issue I'm trying to address is - inconsistency within swiotlb > > dma_map_ops, where (1) any wide mask is silently accepted, but (2) then > > mask is used to decide if bounce buffers are needed or not. This > > inconsistency causes NVMe+R-Car cobmo not working (and breaking memory > > instead). > > The fundamental underlying problem is the "any wide mask is silently > accepted" part, and that applies equally to IOMMU ops as well. It's a much rarer problem for the IOMMU case though, because it only impacts devices that are restricted to addressing of less than 32-bits. If you have an IOMMU enabled, the dma-mapping interface does not care if the device can do wider than 32 bit addressing, as it will never hand out IOVAs above 0xffffffff. > > I just can't think out what similar issue iommu can have. > > Do you mean that in iommu case, mask also must not be set to whatever > > wider than initial value? Why? What is the use of mask in iommu case? Is > > there any real case when iommu can't address all memory existing in the > > system? > > There's a very subtle misunderstanding there - the DMA mask does not > describe the memory a device can address, it describes the range of > addresses the device is capable of generating. Yes, in the non-IOMMU > case they are equivalent, but once you put an IOMMU in between, the > problem is merely shifted from "what range of physical addresses can > this device access" to "what range of IOVAs is valid to give to this > device" - the fact that those IOVAs can map to any underlying physical > address only obviates the need for any bouncing at the memory end; it > doesn't remove the fact that the device has a hardware addressing > limitation which needs to be accommodated. > > The thread Will linked to describes that equivalent version of your > problem - the IOMMU gives the device 48-bit addresses which get > erroneously truncated because it doesn't know that only 42 bits are > actually wired up. That situation still requires the device's DMA mask > to correctly describe its addressing capability just as yours does. That problem should only impact virtual machines which have a guest bus address space covering more than 42 bits of physical RAM, whereas the problem we have with swiotlb is for the dma-mapping interface. > > With this direction, semantics of dma mask becomes even more > > questionable. I'd say dma_mask is candidate for removal (or to move to > > swiotlb's or iommu's local area) > > We still need a way for drivers to communicate a device's probed > addressing capability to SWIOTLB, so there's always going to have to be > *some* sort of public interface. Personally, the change in semantics I'd > like to see is to make dma_set_mask() only fail if DMA is entirely > disallowed - in the normal case it would always succeed, but the DMA API > implementation would be permitted to set a smaller mask than requested > (this is effectively what the x86 IOMMU ops do already). With swiotlb enabled, it only needs to fail if the mask does not contain the swiotlb bounce buffer area, either because the start of RAM is outside of the mask, or the bounce area has been allocated at the end of ZONE_DMA and the mask is smaller than ZONE_DMA. Arnd