From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Siddharth Vadapalli <s-vadapalli@ti.com>
Cc: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com,
robh@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, vigneshr@ti.com,
afd@ti.com, srk@ti.com
Subject: Re: [PATCH 3/3] dt-bindings: PCI: ti,j721e-pci-host: Add support for J722S SoC
Date: Wed, 17 Jan 2024 12:35:14 +0100 [thread overview]
Message-ID: <6119a057-0ed9-46f0-9232-3839d7d4b2e6@linaro.org> (raw)
In-Reply-To: <a34eb14b-9944-476a-8b86-e8bb77bcad82@ti.com>
On 17/01/2024 12:24, Siddharth Vadapalli wrote:
>
>
> On 17/01/24 16:06, Krzysztof Kozlowski wrote:
>> On 17/01/2024 11:25, Siddharth Vadapalli wrote:
>>> TI's J722S SoC has one instance of a Gen3 Single Lane PCIe controller.
>>> The controller on J722S SoC is similar to the one present on TI's AM64
>>> SoC, with the difference being that the controller on AM64 SoC supports
>>> up to Gen2 link speed while the one on J722S SoC supports Gen3 link speed.
>>>
>>> Update the bindings with a new compatible for J722S SoC and enforce checks
>>> for "num-lanes" and "max-link-speed".
>>>
>>> Technical Reference Manual of J722S SoC: https://www.ti.com/lit/zip/sprujb3
>>>
>>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
>>> ---
>>> .../devicetree/bindings/pci/ti,j721e-pci-host.yaml | 13 +++++++++++++
>>> 1 file changed, 13 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
>>> index 005546dc8bd4..b7648f7e73c9 100644
>>> --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
>>> +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
>>> @@ -14,6 +14,7 @@ properties:
>>> compatible:
>>> oneOf:
>>> - const: ti,j721e-pcie-host
>>> + - const: ti,j722s-pcie-host
>>> - const: ti,j784s4-pcie-host
>>> - description: PCIe controller in AM64
>>> items:
>>> @@ -134,6 +135,18 @@ allOf:
>>> minimum: 1
>>> maximum: 4
>>>
>>> + - if:
>>> + properties:
>>> + compatible:
>>> + items:
>>
>> enum
>>
>>> + - const: ti,j722s-pcie-host
>>> + then:
>>> + properties:
>>> + max-link-speed:
>>> + const: 3
>>> + num-lanes:
>>> + const: 1
>>
>> Similarly to previous patch: What is the point of all this? You have
>> direct mapping compatible-property, so encode these in the drivers.
>
> Ok. I will drop patches 1 and 2 of this series and only post v2 of this patch
> for adding a new compatible for J722S SoC without any checks for
> "max-link-speed" or "num-lanes" for the new compatible.
Without driver change? So how does it solve my comment. I want to move
all these unnecessary properties to the driver.
Best regards,
Krzysztof
next prev parent reply other threads:[~2024-01-17 11:35 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-17 10:25 [PATCH 0/3] Fix and update ti,j721e-pci-* bindings Siddharth Vadapalli
2024-01-17 10:25 ` [PATCH 1/3] dt-bindings: PCI: ti,j721e-pci-*: Fix check for num-lanes Siddharth Vadapalli
2024-01-17 10:34 ` Krzysztof Kozlowski
2024-01-17 10:47 ` Siddharth Vadapalli
2024-01-17 10:53 ` Krzysztof Kozlowski
2024-01-17 11:11 ` Siddharth Vadapalli
2024-01-17 11:17 ` Krzysztof Kozlowski
2024-01-17 10:25 ` [PATCH 2/3] dt-bindings: PCI: ti,j721e-pci-*: Add checks for max-link-speed Siddharth Vadapalli
2024-01-17 10:35 ` Krzysztof Kozlowski
2024-01-17 10:58 ` Siddharth Vadapalli
2024-01-17 11:00 ` Krzysztof Kozlowski
2024-01-17 11:15 ` Siddharth Vadapalli
2024-01-17 11:19 ` Krzysztof Kozlowski
2024-01-17 11:22 ` Siddharth Vadapalli
2024-01-17 11:34 ` Krzysztof Kozlowski
2024-01-17 10:25 ` [PATCH 3/3] dt-bindings: PCI: ti,j721e-pci-host: Add support for J722S SoC Siddharth Vadapalli
2024-01-17 10:36 ` Krzysztof Kozlowski
2024-01-17 11:24 ` Siddharth Vadapalli
2024-01-17 11:35 ` Krzysztof Kozlowski [this message]
2024-01-17 11:41 ` Siddharth Vadapalli
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