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Mon, 15 Jul 2024 10:37:10 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 46FAb9pT031246 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 15 Jul 2024 10:37:09 GMT Received: from [10.216.4.154] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 15 Jul 2024 03:37:02 -0700 Message-ID: <6124f9e9-3fdf-29b1-128f-c58f5ebe1424@quicinc.com> Date: Mon, 15 Jul 2024 16:06:59 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.9.0 Subject: Re: [PATCH v2 5/6] clk: qcom: Add camera clock controller driver for SM8150 Content-Language: en-US To: Bryan O'Donoghue , Dmitry Baryshkov CC: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Abhishek Sahu , "Rob Herring" , Krzysztof Kozlowski , Conor Dooley , Stephen Boyd , , , , , Ajit Pandey , "Imran Shaik" , Taniya Das , Jagadeesh Kona References: <20240702-camcc-support-sm8150-v2-0-4baf54ec7333@quicinc.com> <20240702-camcc-support-sm8150-v2-5-4baf54ec7333@quicinc.com> From: "Satya Priya Kakitapalli (Temp)" In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: FfaGW4rugQZQSdXkagZQb-Uthemh45ry X-Proofpoint-ORIG-GUID: FfaGW4rugQZQSdXkagZQb-Uthemh45ry X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-15_06,2024-07-11_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 clxscore=1015 malwarescore=0 spamscore=0 suspectscore=0 priorityscore=1501 mlxscore=0 lowpriorityscore=0 impostorscore=0 adultscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2407150083 On 7/11/2024 3:21 PM, Bryan O'Donoghue wrote: > On 10/07/2024 23:10, Dmitry Baryshkov wrote: >>>> - Why is cam_cc_gdsc_clk not modelled in the clock framework? >>> >>> This clock is kept enabled from probe, hence not required to be >>> modelled >>> explicitly. >> Yes, I'm asking why it's kept up enabled from probe rather than via >> clock framework? > > FWIW my preference is to do it as Dmitry is suggesting here. > > I'm not a big fan of hitting the register and leaving it as-is, would > much prefer to move to the model of having the CCF do it - so that for > example the clock appears in the /sys clock summary. > This clock is PoR ON clock and expected to be always enabled from HW perspective, we are just re-ensuring it is ON from probe. Modelling this clock is unnecessary, and we have been following this approach for  gdsc clock in all the recent chipsets, like for example sm8550 camcc. > --- > bod