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Wed, 26 Aug 2026 17:18:21 +0000 Received: from satlexmb07.amd.com (10.181.42.216) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Wed, 26 Aug 2026 12:18:21 -0500 Received: from [172.19.71.207] (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server id 15.2.2562.45 via Frontend Transport; Wed, 26 Aug 2026 12:18:20 -0500 Message-ID: <61586ab4-bbc4-2795-c4c0-1a0299aeea66@amd.com> Date: Wed, 26 Aug 2026 10:18:20 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH v3 1/3] accel/amdxdna: refuse an I/O memory mapping of an imported BO Content-Language: en-US To: =?UTF-8?Q?Christian_K=c3=b6nig?= , "Taimuraz Kaitmazov" , Min Ma , Oded Gabbay CC: Sumit Semwal , Max Zhen , "Sonal Santan" , , , , , "Liang, Wendy" References: <20260813164700.43960-1-taimuraz@kaitmazov.com> <20260813164700.43960-2-taimuraz@kaitmazov.com> <5933effe-ef28-9838-1dd5-dc904be0a3bd@amd.com> <87c9bb85-2514-44ac-a976-e24526c7f76e@amd.com> <4aaae413-ea6d-4865-be67-f352ee23aa4b@amd.com> From: Lizhi Hou In-Reply-To: <4aaae413-ea6d-4865-be67-f352ee23aa4b@amd.com> Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: DInbD85+WRZO2r7WQ+BGbO+IXWXlH+L+6VNPqfg5joo7FU/1zNwWxVByO60SWdvZDfmME1cdkETZXvuDbl5Ic3ukHlS4KjYJzm5T07nkdq8b0Is0E2sVp2bIw1eOBxtMGJopWERFH9/+hdaLmvWXVcdvhPaOQITBUGf7jEGulFuEWTXHHTTws29+g4WmitqtG/XTpWM7b9gAEvCJn5IEHjzjwAjKPU6P09xwEjyiV3sVm913SIQ+BlDL4N6rhF3qsyAzx2PBOfTGiM6feDGAzt0brYg1v+ifObslnfIO+nzNVFnmH7LwPrvHwHnOkcEjrP4LhjpWc8CJugzuwx7wWAKKq61K4+CQfDYB/4+lsM8RFkYuGmXjZvr+LMkKTGdUfwRhvJ0+VZhVu0ltLvNaKAUSeNEPE23BIWFe4BQM4AJbULV1U0NP1uhGe9gyoVuV X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Aug 2026 17:18:21.9390 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 50702b05-150e-4cfb-aa14-08df039607c2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[149.199.90.133];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000066EC.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5959 On 8/26/26 01:37, Christian König wrote: > On 8/24/26 18:08, Lizhi Hou wrote: >> On 8/24/26 07:06, Christian König wrote: >>> On 8/17/26 19:53, Lizhi Hou wrote: >>>> On 8/13/26 09:46, Taimuraz Kaitmazov wrote: >>>>> amdxdna_gem_obj_vmap() takes whatever dma_buf_vmap() returns and only >>>>> rejects a NULL vaddr. iosys_map is discriminated by is_iomem, so an >>>>> exporter answering with an I/O mapping leaves a void __iomem pointer in >>>>> abo->mem.kva, which amdxdna_cmd_set_error() memsets and memcpys through. >>>>> >>>>> amdxdna_drm_va_tbl takes a dmabuf_fd, so such a BO can be any exporter's >>>>> buffer. amdgpu cannot reach this: its .pin forces GTT for a non peer to >>>>> peer attachment like ours. An exporter on drm_gem_prime_dmabuf_ops has >>>>> no .pin, and drm_gem_ttm_vmap() answers iomem for a VRAM resident >>>>> object, so an NPU paired with nouveau or radeon does. >>>>> >>>>> Refuse the mapping. vmw_gem_vmap() does the same; unlike that one this >>>>> path is reachable from an unprivileged ioctl, so it does not warn. >>>>> >>>>> Signed-off-by: Taimuraz Kaitmazov >>>>> --- >>>>>    drivers/accel/amdxdna/amdxdna_gem.c | 10 ++++++++-- >>>>>    1 file changed, 8 insertions(+), 2 deletions(-) >>>>> >>>>> diff --git a/drivers/accel/amdxdna/amdxdna_gem.c b/drivers/accel/amdxdna/amdxdna_gem.c >>>>> index 1f190b319bb..b66ec9e4828 100644 >>>>> --- a/drivers/accel/amdxdna/amdxdna_gem.c >>>>> +++ b/drivers/accel/amdxdna/amdxdna_gem.c >>>>> @@ -683,10 +683,16 @@ static int amdxdna_gem_obj_vmap(struct drm_gem_object *obj, struct iosys_map *ma >>>>>          dma_resv_assert_held(obj->resv); >>>>>    -    if (is_import_bo(abo)) >>>>> +    if (is_import_bo(abo)) { >>>>>            ret = dma_buf_vmap(abo->dma_buf, map); >>> Mhm, why does amdxdna a vmap in the first place? For some workaround? >> This is used for flushing the imported BO before. Based on our discussion before, the driver should not flush imported BO, so this becomes a invalid case. >> >> On the other hand, vmap on a io_mem should not happen. So I suggested to move the check to amdxdna_gem_vmap() for an extra check. > Oh my, you should not use a vmap to flush CPU caches even if you own that GEM buffer! That is as buggy as it can be and most likely doesn't work 100% reliable. We know that it would be problem on non-x86 architectures. And currently the device is X86 only. Is flushing through vmap buggy on x86 as well? To make the flush running on all architectures,  I can remove the vmap completely here and only use drm_clflush_pages. Does this sound right? > > What is the complete command submission flow here? So the submission flow is roughly:  alloc bo -> mmap BO -> write BO content (and flush CPU cache by user space runtime) -> submit/wait io command. Thanks, Lizhi > > Regards, > Christian. > >> >> Thanks, >> >> Lizhi >> >>> Usually DMA-buf only provides that framebuffer emulation scanout inside the kernel. >>> >>> On the other hand as far as I can see that here should work correctly. >>> >>> Regards, >>> Christian. >>> >>>>> -    else >>>>> +        /* Callers use mem.kva as an ordinary kernel address. */ >>>>> +        if (!ret && map->is_iomem) { >>>>> +            dma_buf_vunmap(abo->dma_buf, map); >>>>> +            return -EOPNOTSUPP; >>>>> +        } >>>> Thanks for the fix. The 'is_iomem' check should be moved to amdxdna_gem_vmap() to cover all the cases. >>>> >>>> Lizhi >>>> >>>>> +    } else { >>>>>            ret = drm_gem_shmem_object_vmap(obj, map); >>>>> +    } >>>>>        if (ret) >>>>>            return ret; >>>>>        if (!map->vaddr)