From: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
To: Taniya Das <taniya.das@oss.qualcomm.com>,
Bjorn Andersson <andersson@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney@redhat.com>,
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org,
Ajit Pandey <ajit.pandey@oss.qualcomm.com>,
Imran Shaik <imran.shaik@oss.qualcomm.com>
Subject: Re: [PATCH 1/2] clk: qcom: gpucc-glymur: Mark the GPU CX GDSC as votable
Date: Wed, 5 Aug 2026 16:17:17 +0530 [thread overview]
Message-ID: <6166c963-e9e7-4442-ad84-976d389b4663@oss.qualcomm.com> (raw)
In-Reply-To: <20260801-kaanapali-gpu-voteable-v1-1-fe804d24d2e9@oss.qualcomm.com>
On 8/1/2026 11:01 PM, Taniya Das wrote:
> The GPU CX GDSC on Glymur is a votable power domain and hence should
> not be polled for power-off status during GDSC disable. Also, its
> power-on status should be read from the GDS hardware control register.
>
> Accommodate this by removing POLL_CFG_GDSCR and adding the VOTABLE
> flag for the GPU CX GDSC, similar to other platforms (e.g. SM8750 and
> Milos).
>
Reviewed-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
Thanks,
Jagadeesh
next prev parent reply other threads:[~2026-08-05 10:47 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-01 17:31 [PATCH 0/2] clk: qcom: Mark the GPU CX GDSC as votable for Glymur and Kaanapali Taniya Das
2026-08-01 17:31 ` [PATCH 1/2] clk: qcom: gpucc-glymur: Mark the GPU CX GDSC as votable Taniya Das
2026-08-05 10:47 ` Jagadeesh Kona [this message]
2026-08-01 17:31 ` [PATCH 2/2] clk: qcom: gpucc-kaanapali: " Taniya Das
2026-08-05 10:48 ` Jagadeesh Kona
2026-08-10 18:46 ` [PATCH 0/2] clk: qcom: Mark the GPU CX GDSC as votable for Glymur and Kaanapali Bjorn Andersson
2026-08-31 20:21 ` Bjorn Andersson
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