From: Srirangan Madhavan <smadhavan@nvidia.com>
To: Alison Schofield <alison.schofield@intel.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Dave Jiang <dave.jiang@intel.com>,
Davidlohr Bueso <dave@stgolabs.net>,
Ira Weiny <ira.weiny@intel.com>,
Jonathan Cameron <jic23@kernel.org>,
Vishal Verma <vishal.l.verma@intel.com>,
linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: Alex Williamson <alex.williamson@redhat.com>,
vsethi@nvidia.com, alwilliamson@nvidia.com,
Sai Yashwanth Reddy Kancherla <skancherla@nvidia.com>,
Vishal Aslot <vaslot@nvidia.com>,
Manish Honap <mhonap@nvidia.com>, Jiandi An <jan@nvidia.com>,
Richard Cheng <icheng@nvidia.com>,
linux-tegra@vger.kernel.org
Subject: Re: [PATCH v12 00/12] PCI/CXL: Add CXL reset support for Type 2 devices
Date: Thu, 10 Sep 2026 00:31:02 -0700 [thread overview]
Message-ID: <61d5efc2-bb17-4f2c-89e8-2433fc85ca2b@nvidia.com> (raw)
In-Reply-To: <20260910070808.1444264-1-smadhavan@nvidia.com>
On 9/10/26 12:07 AM, Srirangan Madhavan wrote:
> v12 changes from v11 [2]:
> - Reject cxl_reset and cxl_bus reset when the PF has enabled VFs,
> including VFs enabled after reset-method probing.
> - Require CXL Reset Memory Clear support and request memory clearing so
> the generic PCI reset does not preserve tenant memory.
> - Cache the CXL Device DVSEC control register during early PCI discovery
> and restore its CXL.cache and CXL.mem enable bits after CXL Reset and
> CXL bus reset.
> - Initialize the early PCI HDM cache only from pci_bus_add_device(),
> removing the later CXL core retry and its lifecycle locking.
> - Reapply and verify a cached HDM decoder lock after decoder restoration
> and commit, while leaving surviving locked committed state unchanged.
> - Convert temporary early HDM-cache ownership to scoped cleanup.
> - Document the reset-safety contract, including the iomem ownership
> requirement and the limits around memory offlining and mapping
> revocation.
Hi Bjorn, Dave, and CXL maintainers
Based on the review feedback so far, I believe the overall design is in
reasonable shape. I have addressed the feedback received so far in v12.
The series passes the kernel/module build checks and both cxl_reset and
cxl_bus testing on a target system.
I would appreciate any guidance on remaining issues or additional
changes needed to move the series further toward acceptance.
--
Regards,
Srirangan
prev parent reply other threads:[~2026-09-10 7:31 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-10 7:07 Srirangan Madhavan
2026-09-10 7:07 ` [PATCH v12 01/12] cxl: Move HDM decoder programming helpers Srirangan Madhavan
2026-09-10 7:07 ` [PATCH v12 02/12] cxl: Make HDM commit helpers available to reset code Srirangan Madhavan
2026-09-10 7:07 ` [PATCH v12 03/12] cxl: Share HDM decoder decode logic Srirangan Madhavan
2026-09-10 7:08 ` [PATCH v12 04/12] cxl: Cache decoder settings on PCI devices Srirangan Madhavan
2026-09-10 7:08 ` [PATCH v12 05/12] cxl: Cache endpoint decoder settings during PCI enumeration Srirangan Madhavan
2026-09-10 7:08 ` [PATCH v12 06/12] cxl: Add CXL Device Reset helper Srirangan Madhavan
2026-09-10 7:08 ` [PATCH v12 07/12] cxl: Validate HDM ranges before CXL reset Srirangan Madhavan
2026-09-10 7:08 ` [PATCH v12 08/12] PCI/CXL: Reject CXL Reset on multifunction devices Srirangan Madhavan
2026-09-10 7:08 ` [PATCH v12 09/12] cxl: Restore CXL state after PCI reset Srirangan Madhavan
2026-09-10 7:08 ` [PATCH v12 10/12] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-09-10 7:08 ` [PATCH v12 11/12] Documentation/ABI: Document CXL Reset " Srirangan Madhavan
2026-09-10 7:08 ` [PATCH v12 12/12] PCI/CXL: Restore CXL state after CXL bus reset Srirangan Madhavan
2026-09-10 7:31 ` Srirangan Madhavan [this message]
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