Re: [PATCH kernel 1/3] x86/amd/dr_addr_mask: Cache values in percpu variables

[Andrew Cooper <Andrew.Cooper3@citrix.com>]

On 01/12/2022 16:58, Sean Christopherson wrote:
>> diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
>> index c75d75b9f11a..ec7efcef4e14 100644
>> --- a/arch/x86/kernel/cpu/amd.c
>> +++ b/arch/x86/kernel/cpu/amd.c
>> @@ -1158,6 +1158,11 @@ static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
>>  	return false;
>>  }
>>  
>> +DEFINE_PER_CPU_READ_MOSTLY(unsigned long, dr0_addr_mask);
>> +DEFINE_PER_CPU_READ_MOSTLY(unsigned long, dr1_addr_mask);
>> +DEFINE_PER_CPU_READ_MOSTLY(unsigned long, dr2_addr_mask);
>> +DEFINE_PER_CPU_READ_MOSTLY(unsigned long, dr3_addr_mask);
>> +
>>  void set_dr_addr_mask(unsigned long mask, int dr)
>>  {
>>  	if (!boot_cpu_has(X86_FEATURE_BPEXT))
>> @@ -1166,17 +1171,44 @@ void set_dr_addr_mask(unsigned long mask, int dr)
>>  	switch (dr) {
>>  	case 0:
>>  		wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0);
> LOL, I'd love to hear how MSR_F16H_DR0_ADDR_MASK ended up with a completely
> different MSR index.

(Very) back in the day, this is was a special for %dr0 only.

When the feature was made architectural (CPUID.80000001.ecx[26] "data
breakpoint extensions"), 3 more registered needed to be allocated. 

There's also CPUID.80000001.ecx[30] "Address Mask Extensions" which mean
"all 32 bits work", where previously only bits above 12 took effect. 
I.e. you can now match within the same page.

And somewhere I'm pretty sure there's another bit (New in Zen2/Rome ?)
saying that all 64 bits work, but I can't actually locate the CPUID bit.

~Andrew