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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: i2gMiQx4rm1Q5p-zrA6b_j3vB41F-CXG X-Proofpoint-GUID: i2gMiQx4rm1Q5p-zrA6b_j3vB41F-CXG X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzEzMDEyMSBTYWx0ZWRfX2LSWYN74BSyp qeG58tL4x5oEkAmoKoi2uqdil4dl6TWa0rtdEvy+Y2t6gBc3RUh7LxR3VcJkF1HfE46mveI/W1J nbRC9bBheydlHUnUkA4bzfV3YsyDvIWfaPHJuKxEFWU6QVeaO87HnnRwq35H4hV+bETGazWzUr0 fZKCPRVLgAeuHJ3K/MamcqyyZ9LI0hZ6+dG3vaPp1Illdfb+Xpp6b6w3fMwsMW6tVjhkb/d4h91 +MJj//lva232AR2AyoGUJlX0hYv4E55IdVyfqx1kSJBVKNOMQWIEOMsi6jmQdbFtQKXrZ3JBfXu 76E0k1Q3Z8eBRwFID3mR2NqXm/FCunLco8gERIjImUGsGcwoy4VQM352soPD3woyRuvGAnr8YMk ZyWWcJgB7ymZ3HLeOgkoOJwjzrQWa6A+ZFDRdL69tYsEudas4mJvX+9UJCmgS8DBF4Yp3sDaOvI 26Xbsqme0rEeBl2jvog== X-Authority-Analysis: v=2.4 cv=BpiQAIX5 c=1 sm=1 tr=0 ts=69b42a6f cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=EbT04XG53EGSLiegdi54Hw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=NEAV23lmAAAA:8 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=H73U6gjSJfwdDiR_EpgA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-13_02,2026-03-13_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 phishscore=0 adultscore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 spamscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603130121 On 3/13/2026 8:32 PM, Dmitry Baryshkov wrote: > On Fri, Mar 13, 2026 at 06:49:35PM +0530, Vikash Garodia wrote: >> Kaanapali SOC brings in the new generation of video IP i.e iris4. When >> compared to previous generation, iris3x, it has, >> - separate power domains for stream and pixel processing hardware blocks >> (bse and vpp). >> - additional power domain for apv codec. >> - power domains for individual pipes (VPPx). >> - different clocks and reset lines. >> >> This patch depends on >> https://github.com/devicetree-org/dt-schema/pull/184/changes/d341298d62805bc972dfba691da6b3b62aa3ff15 >> >> Nacked-by: Krzysztof Kozlowski >> Signed-off-by: Vikash Garodia >> --- >> .../bindings/media/qcom,kaanapali-iris.yaml | 254 +++++++++++++++++++++ >> include/dt-bindings/media/qcom,kaanapali-iris.h | 18 ++ >> 2 files changed, 272 insertions(+) > >> + >> + video-codec@2000000 { >> + compatible = "qcom,kaanapali-iris"; >> + reg = <0x02000000 0xf0000>; >> + >> + clocks = <&gcc_video_axi0_clk>, >> + <&video_cc_mvs0c_clk>, >> + <&video_cc_mvs0_clk>, >> + <&gcc_video_axi1_clk>, >> + <&video_cc_mvs0c_freerun_clk>, >> + <&video_cc_mvs0_freerun_clk>, >> + <&video_cc_mvs0b_clk>, >> + <&video_cc_mvs0_vpp0_clk>, >> + <&video_cc_mvs0_vpp1_clk>, >> + <&video_cc_mvs0a_clk>; >> + clock-names = "iface", >> + "core", >> + "vcodec0_core", >> + "iface1", >> + "core_freerun", >> + "vcodec0_core_freerun", >> + "vcodec_bse", >> + "vcodec_vpp0", >> + "vcodec_vpp1", >> + "vcodec_apv"; >> + >> + dma-coherent; >> + >> + interconnects = <&gem_noc_master_appss_proc &config_noc_slave_venus_cfg>, >> + <&mmss_noc_master_video_mvp &mc_virt_slave_ebi1>; >> + interconnect-names = "cpu-cfg", >> + "video-mem"; >> + >> + interrupts = ; >> + >> + iommu-map = , >> + , >> + , > > It think we still haven't settled on letting iommu-map to have several > entries for a single function. I have described the hardware aspects in the discussion [1], if there is any alternate way to handle this, we can discuss in the same discussion. [1] https://lore.kernel.org/all/21fda4d2-72e1-4e5b-aee0-a799886f53b7@oss.qualcomm.com/ > >> + , >> + , >> + , >> + , >> + , >> + ; >> + >> + memory-region = <&video_mem>; >> + >> + operating-points-v2 = <&iris_opp_table>; >> + >> + power-domains = <&video_cc_mvs0c_gdsc>, >> + <&video_cc_mvs0_gdsc>, >> + <&rpmhpd RPMHPD_MXC>, >> + <&rpmhpd RPMHPD_MMCX>, >> + <&video_cc_mvs0_vpp0_gdsc>, >> + <&video_cc_mvs0_vpp1_gdsc>, >> + <&video_cc_mvs0a_gdsc>; >> + power-domain-names = "venus", >> + "vcodec0", >> + "mxc", >> + "mmcx", >> + "vpp0", >> + "vpp1", >> + "apv"; >> + >> + resets = <&gcc_video_axi0_clk_ares>, >> + <&gcc_video_axi1_clk_ares>, >> + <&video_cc_mvs0c_freerun_clk_ares>, >> + <&video_cc_mvs0_freerun_clk_ares>; >> + reset-names = "bus0", >> + "bus1", >> + "core", >> + "vcodec0_core"; >> + >> + iris_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-240000000 { >> + opp-hz = /bits/ 64 <240000000 240000000 240000000 360000000>; >> + required-opps = <&rpmhpd_opp_low_svs_d1>, >> + <&rpmhpd_opp_low_svs_d1>; > > It's a DT and not the schema question, but please cross-check the OPP > points here. If I understand Taniya correctly, we should be using > corners from the PLL type rather than from the video_cc clock plan (they > differ for some reason). Downstream videocc driver also should have > correct rail corners for the PLLs. > >> + }; >> + >