From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59622C433E1 for ; Thu, 27 Aug 2020 08:28:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 28BC720738 for ; Thu, 27 Aug 2020 08:28:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728236AbgH0I2w convert rfc822-to-8bit (ORCPT ); Thu, 27 Aug 2020 04:28:52 -0400 Received: from eu-smtp-delivery-151.mimecast.com ([207.82.80.151]:28213 "EHLO eu-smtp-delivery-151.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727883AbgH0I2u (ORCPT ); Thu, 27 Aug 2020 04:28:50 -0400 Received: from AcuMS.aculab.com (156.67.243.126 [156.67.243.126]) (Using TLS) by relay.mimecast.com with ESMTP id uk-mta-114-cyAKyHkbOAOvWmpU6WpmIQ-1; Thu, 27 Aug 2020 09:28:46 +0100 X-MC-Unique: cyAKyHkbOAOvWmpU6WpmIQ-1 Received: from AcuMS.Aculab.com (fd9f:af1c:a25b:0:43c:695e:880f:8750) by AcuMS.aculab.com (fd9f:af1c:a25b:0:43c:695e:880f:8750) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 27 Aug 2020 09:28:45 +0100 Received: from AcuMS.Aculab.com ([fe80::43c:695e:880f:8750]) by AcuMS.aculab.com ([fe80::43c:695e:880f:8750%12]) with mapi id 15.00.1347.000; Thu, 27 Aug 2020 09:28:45 +0100 From: David Laight To: 'Thomas Gleixner' , Alexander Graf , X86 ML CC: Andy Lutomirski , LKML , Andrew Cooper , "Paul E. McKenney" , Alexandre Chartre , Frederic Weisbecker , Paolo Bonzini , Sean Christopherson , Masami Hiramatsu , Petr Mladek , Steven Rostedt , Joel Fernandes , Boris Ostrovsky , Juergen Gross , Mathieu Desnoyers , Josh Poimboeuf , "Will Deacon" , Tom Lendacky , Wei Liu , Michael Kelley , Jason Chen CJ , Zhao Yakui , "Peter Zijlstra (Intel)" , Avi Kivity , "Herrenschmidt, Benjamin" , "robketr@amazon.de" , "amos@scylladb.com" , Brian Gerst , "stable@vger.kernel.org" , "Alex bykov" Subject: RE: x86/irq: Unbreak interrupt affinity setting Thread-Topic: x86/irq: Unbreak interrupt affinity setting Thread-Index: AQHWe+aKb+AhwM2rPkq6/MK3Hcp5nKlK5iEA///7/wCAALxiUA== Date: Thu, 27 Aug 2020 08:28:45 +0000 Message-ID: <620d67af76554a558061c8df5e2cb038@AcuMS.aculab.com> References: <20200826115357.3049-1-graf@amazon.com> <87k0xlv5w5.fsf@nanos.tec.linutronix.de> <87blixuuny.fsf@nanos.tec.linutronix.de> <873649utm4.fsf@nanos.tec.linutronix.de> <87wo1ltaxz.fsf@nanos.tec.linutronix.de> <87ft89kqmd.fsf@nanos.tec.linutronix.de> In-Reply-To: <87ft89kqmd.fsf@nanos.tec.linutronix.de> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.202.205.107] MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=C51A453 smtp.mailfrom=david.laight@aculab.com X-Mimecast-Spam-Score: 0.002 X-Mimecast-Originator: aculab.com Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Thomas Gleixner > Sent: 26 August 2020 23:08 ... > > I suspect that it is much more 'racy' than that for PCI-X interrupts. > > On the hardware side there is an interrupt disable bit, and address > > and a value. > > To raise an interrupt the hardware must write the value to the > > address. > > Really? Yep, anyone with write access to the msi-x table can get the device to write to any physical location (allowed by any IOMMU) instead of raising an interrupt. > > If the cpu needs to move an interrupt both the address and value > > need changing, but the cpu wont write the address and value using > > the same TLP, so the hardware could potentially write a value to > > the wrong address. > > Now I understand finally why msi_set_affinity() in x86 has to be so > convoluted. Updating the registers should be much the same on all architectures. I probably should have looked at what msi_set_affinity() does before deciding which order the fpga logic should read the four 32bit registers in; but they are read in increasing order - so enable bit last. David - Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK Registration No: 1397386 (Wales)