From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13E58C2BA19 for ; Wed, 22 Apr 2020 02:13:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EA931206D5 for ; Wed, 22 Apr 2020 02:13:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726430AbgDVCNy (ORCPT ); Tue, 21 Apr 2020 22:13:54 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:2827 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726024AbgDVCNx (ORCPT ); Tue, 21 Apr 2020 22:13:53 -0400 Received: from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 2520FFF88CC5973942B7; Wed, 22 Apr 2020 10:13:51 +0800 (CST) Received: from [127.0.0.1] (10.173.220.25) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.487.0; Wed, 22 Apr 2020 10:13:41 +0800 Subject: Re: [PATCH v1 1/6] arm64: Detect the ARMv8.4 TTL feature To: Christoph Hellwig , Peter Zijlstra CC: , , , , , , , , , , , , , , , , , , , , , , , , References: <20200403090048.938-1-yezhenyu2@huawei.com> <20200403090048.938-2-yezhenyu2@huawei.com> <20200421165346.GA11171@infradead.org> <20200421171328.GW20730@hirez.programming.kicks-ass.net> <20200421171641.GA25391@infradead.org> From: Zhenyu Ye Message-ID: <62414595-298a-da11-28eb-36ad1dc59e65@huawei.com> Date: Wed, 22 Apr 2020 10:13:39 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.3.0 MIME-Version: 1.0 In-Reply-To: <20200421171641.GA25391@infradead.org> Content-Type: text/plain; charset="gbk" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.173.220.25] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2020/4/22 1:16, Christoph Hellwig wrote: > On Tue, Apr 21, 2020 at 07:13:28PM +0200, Peter Zijlstra wrote: >> On Tue, Apr 21, 2020 at 09:53:46AM -0700, Christoph Hellwig wrote: >>> On Fri, Apr 03, 2020 at 05:00:43PM +0800, Zhenyu Ye wrote: >>>> From: Marc Zyngier >>>> >>>> In order to reduce the cost of TLB invalidation, the ARMv8.4 TTL >>>> feature allows TLBs to be issued with a level allowing for quicker >>>> invalidation. >>> >>> What does "issued with a level" mean? >> >> What I understood it to be is page-size based on page-table hierarchy. >> Just like we have on x86, 4k, 2m, 1g etc.. >> >> So where x86 INVLPG will tear down any sized page for the address given, >> you can now day, kill me the PMD level translation for @addr. >> >> Power9 radix also has things like this. > > Maybe this needs to be spelled out a little more? The current commit > log sounds like paper generated by a neural network. > Emm... This patch was synchronized from Marc's NV series [1]. "issued with a level" means the TLBs now can get which levels of page tables the @addr is in. You can also understand it as page-size as Peter said above, just like pud, pmd, pte... Anyway, I will explain this in more detail. Thanks, Zhenyu