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Sun, 25 Feb 2018 08:01:12 -0500 Received: from mail-wr0-f171.google.com ([209.85.128.171]:40870 "EHLO mail-wr0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751729AbeBYNBK (ORCPT ); Sun, 25 Feb 2018 08:01:10 -0500 X-Google-Smtp-Source: AH8x224xKp3btfvGTMefj8oppOvDu4txnFSDAeyFWJtkq9gl+bWHOlXUU1tHgqO8BZhKNTlmnBANpw== Subject: Re: [PATCH 08/12] xhci: Add Intel extended cap / otg phy mux handling To: Andy Shevchenko Cc: Darren Hart , Andy Shevchenko , MyungJoo Ham , Chanwoo Choi , Mathias Nyman , Heikki Krogerus , Greg Kroah-Hartman , Platform Driver , Linux Kernel Mailing List , USB References: <20180216104751.8371-1-hdegoede@redhat.com> <20180216104751.8371-9-hdegoede@redhat.com> From: Hans de Goede Message-ID: <6244675b-715b-bf8a-9f35-212d6a37308b@redhat.com> Date: Sun, 25 Feb 2018 14:01:06 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-usb-owner@vger.kernel.org X-Mailing-List: linux-usb@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-Mailing-List: linux-kernel@vger.kernel.org List-ID: Hi, On 16-02-18 14:53, Andy Shevchenko wrote: > On Fri, Feb 16, 2018 at 12:47 PM, Hans de Goede wrote: >> The xHCI controller on various Intel SoCs has an extended cap mmio-range >> which contains registers to control the muxing to the xHCI (host mode) >> or the dwc3 (device mode) and vbus-detection for the otg usb-phy. >> >> Having a role-sw driver included in the xhci code (under drivers/usb/host) >> is not desirable. So this commit adds a simple handler for this extended >> capability, which creates a platform device with the caps mmio region as >> resource, this allows us to write a separate platform role-sw driver for >> the role-switch. >> >> Note this commit adds a call to the new xhci_ext_cap_init() function >> to xhci_pci_probe(), it is added here because xhci_ext_cap_init() must >> be called only once. If in the future we also want to handle ext-caps >> on non pci xHCI HCDs from xhci_ext_cap_init() a call to it should also >> be added to other bus probe paths. > > SPDX? Ack, fixed for v2. >> +/* >> + * XHCI extended capability handling >> + * >> + * Copyright (c) 2017 Hans de Goede >> + * >> + * This program is free software; you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License version 2 as >> + * published by the Free Software Foundation. >> + */ > >> + pdev = platform_device_alloc("intel_xhci_usb_sw", PLATFORM_DEVID_NONE); > > Perhaps, > > #define USB_SW_DRV_NAME "..." Ack, fixed for v2. >> + if (!pdev) { >> + xhci_err(xhci, "couldn't allocate intel_xhci_usb_sw pdev\n"); > > ...and re-use it everywhere here. > > pdev -> platform device. > >> + return -ENOMEM; >> + } >> + >> + res.start = hcd->rsrc_start + cap_offset; >> + res.end = res.start + 0x3ff; > > Is this magic always the same? Where its value comes from? > At least define with comment. Ack, I've added a USB_SW_RESOURCE_SIZE #define for this for v2. >> +int xhci_ext_cap_init(struct xhci_hcd *xhci) >> +{ >> + void __iomem *base = &xhci->cap_regs->hc_capbase; >> + u32 cap_offset, val; >> + int ret; >> + >> + cap_offset = xhci_find_next_ext_cap(base, 0, 0); >> + >> + while (cap_offset) { >> + val = readl(base + cap_offset); >> + >> + switch (XHCI_EXT_CAPS_ID(val)) { >> + case XHCI_EXT_CAPS_VENDOR_INTEL: >> + if (xhci->quirks & XHCI_INTEL_USB_ROLE_SW) { > >> + ret = xhci_create_intel_xhci_sw_pdev( >> + xhci, cap_offset); > > Can we leave xhci on previous line? Fixed for v2. >> + if (ret) >> + return ret; >> + } >> + break; >> + } >> + cap_offset = xhci_find_next_ext_cap(base, cap_offset, 0); >> + } >> + >> + return 0; >> +} > > Regards, Hans