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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b6d85413b88sm1692077866b.55.2025.10.30.03.56.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 30 Oct 2025 03:56:26 -0700 (PDT) Message-ID: <625c1a6f-3449-48e4-b217-725bc2bda6e4@oss.qualcomm.com> Date: Thu, 30 Oct 2025 11:56:23 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 04/24] arm64: dts: qcom: glymur: Add QUPv3 configuration for serial engines To: Jyothi Kumar Seerapu , Pankaj Patil , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250925-v3_glymur_introduction-v1-0-24b601bbecc0@oss.qualcomm.com> <20250925-v3_glymur_introduction-v1-4-24b601bbecc0@oss.qualcomm.com> <8828946b-3979-4e7b-a11c-740d8a6253ce@oss.qualcomm.com> <5931e2eb-5f2d-49bb-8b9c-b49f77d7fcbf@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <5931e2eb-5f2d-49bb-8b9c-b49f77d7fcbf@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=aaVsXBot c=1 sm=1 tr=0 ts=6903445c cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=EyQ-x-pg-_UwrLxwVegA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=OIgjcC2v60KrkQgK7BGD:22 X-Proofpoint-ORIG-GUID: F5vT-Ba5un5ebItW8uY-4U9PjNDUsbxV X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDMwMDA4OSBTYWx0ZWRfXypai96WUFSd/ wxajBQ1S465/IPGEmFtYzvLhjZG1X9eaMfHaXafIPCNdwe0Wy7hKyz9gXHdO8XKoiDJQbxAdL5J Gh93H6RWkoCK0A11yJ7Mf3VY/bOinj0dZtNFZ1XHIimQaVHaBjk4Ux5q3KoSsh8DF1lpbhTM9gY NLW8GH1KVyoGz0uoR4qHNMvP2Vz+jgQG/ryNUijViNKl1l83HhuqArmdh+7wTnc7aGfGx9zqZgT 44DcU0S0HLQ2VlWOQZzeVM/xvsHgiVsPBu9zDTtLwNS/nEoblGnm9OHYpz7M8CF5EUQ3/qhjhTM AIfLgTwa4tBM7aQgSkoj3Q5LefEVaJSRXOxNSu45/5HVOqPsKLU0zzr8RGCPDDRw9S9wYcE72Mw Jd/QV1DaHaMjgG/60AY+R1wf2QQN8A== X-Proofpoint-GUID: F5vT-Ba5un5ebItW8uY-4U9PjNDUsbxV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-10-30_03,2025-10-29_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 impostorscore=0 suspectscore=0 spamscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2510300089 On 10/15/25 12:24 PM, Jyothi Kumar Seerapu wrote: > > On 9/25/2025 3:48 PM, Konrad Dybcio wrote: >> On 9/25/25 8:32 AM, Pankaj Patil wrote: >>> From: Jyothi Kumar Seerapu >>> >>> Add device tree support for QUPv3 serial engine protocols on Glymur. >>> Glymur has 24 QUP serial engines across 3 QUP wrappers, each with >>> support of GPI DMA engines. >>> >>> Signed-off-by: Jyothi Kumar Seerapu >>> Signed-off-by: Pankaj Patil >>> --- >> [...] >> >>> +        gpi_dma2: dma-controller@800000 { >>> +            compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; >>> +            reg = <0 0x00800000 0 0x60000>; >>> +            interrupts = , >>> +                     , >>> +                     , >>> +                     , >>> +                     , >>> +                     , >>> +                     , >>> +                     , >>> +                     , >>> +                     , >>> +                     , >>> +                     , >>> +                     , >>> +                     , >>> +                     , >>> +                     ; >>> +            dma-channels = <16>; >>> +            dma-channel-mask = <0x3f>; >>> +            #dma-cells = <3>; >>> +            iommus = <&apps_smmu 0xd76 0x0>; >>> +            status = "ok"; >> this is implied by default, drop > > Hi Konard, > > Do you mean we should remove the |status| property for all QUPs and GPI_DMAs from the common device tree (SOC) and enable them only in the board-specific device tree files? Generally you don't need to specify status = "okay" at all (unless someone set the status to "disabled"/"reserved" before, such as the initial definition in the included DTSI) But I believe you should be able to keep these enabled everywhere, as the secure configuration which (dis)allows this is SoC-bound 99.9% of the time Konrad