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Sun, 26 Oct 2025 02:33:59 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFQBERQ6dlt5UHcYOlT6Y1tPbrDH52NPHs0vo71kb86ovM01aE0uB9o33e/ODR94nDiuD9/HA== X-Received: by 2002:a17:903:2a8d:b0:27e:eee6:6df2 with SMTP id d9443c01a7336-292d3fb7f47mr128134215ad.7.1761471239159; Sun, 26 Oct 2025 02:33:59 -0700 (PDT) Received: from [192.168.0.3] ([49.205.244.82]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29498cf3f4asm45343295ad.11.2025.10.26.02.33.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 26 Oct 2025 02:33:58 -0700 (PDT) Message-ID: <6292dd07-0a74-4773-ad5f-b737b2f848dd@oss.qualcomm.com> Date: Sun, 26 Oct 2025 15:03:51 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V2 2/4] arm64: dts: qcom: sm8750: Add SDC2 nodes for sm8750 soc To: Abel Vesa Cc: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, quic_nguyenb@quicinc.com, quic_rampraka@quicinc.com, quic_pragalla@quicinc.com, quic_sayalil@quicinc.com, quic_nitirawa@quicinc.com, quic_bhaskarv@quicinc.com, kernel@oss.qualcomm.com References: <20251023112924.1073811-1-sarthak.garg@oss.qualcomm.com> <20251023112924.1073811-3-sarthak.garg@oss.qualcomm.com> Content-Language: en-US From: Sarthak Garg In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDI2MDA4OCBTYWx0ZWRfXwi+fZjVR9nEJ WdZ/J36AYKgig+FACMpKTz8JXoySJcH7wLui0lc0UQTvC8ow9BM03HucZdAFjRdYyFPKMPaGIow FORjSPYjiq8BZmoR7lrSgiJs7Tn+9XZ3t6vHM3kIewXGv97ksAVvi1RWxeZ2zZOHAhC7U2fpkEh AV2903BrHOgvnEVAp3h03KKIddRTqnoYvGPfYQXicBH5Vx86vSw/D+LJdC95kIBiWfyPrcB2Okd J26VSu7qnuz6oHjVXKxQGvxJxC6DTPgvxvwTO+GzJCdkV+KI7N7bePngd3ZBj18nn3cB8+0ZgxT DAsipwu7mcK+P1OAx+PWyleNlB7FshiQOCqJPr7XTNOGOBN9m4w/yJRAJ6fbzlJejlwx4w+O2Vz DRdJu5GAzVbbLTqNSU8ECdEza6tyOQ== X-Proofpoint-ORIG-GUID: QV3xkFQR6GOK2Jqz2stsrX-5xN_srkf9 X-Proofpoint-GUID: QV3xkFQR6GOK2Jqz2stsrX-5xN_srkf9 X-Authority-Analysis: v=2.4 cv=WqMm8Nfv c=1 sm=1 tr=0 ts=68fdeb08 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=bVPtsstaAh+Xhvtfxu+pEg==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=sFmbwog37gvI7kGm1A4A:9 a=KKStjhyEKkBOW3-R:21 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-26_04,2025-10-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 impostorscore=0 spamscore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510020000 definitions=main-2510260088 On 10/23/2025 5:44 PM, Abel Vesa wrote: > On 25-10-23 16:59:22, Sarthak Garg wrote: >> Add SD Card host controller for sm8750 soc. >> >> Signed-off-by: Sarthak Garg >> --- >> arch/arm64/boot/dts/qcom/sm8750.dtsi | 68 ++++++++++++++++++++++++++++ >> 1 file changed, 68 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi >> index a82d9867c7cb..1070dc5ea196 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi >> @@ -2060,6 +2060,60 @@ ice: crypto@1d88000 { >> clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; >> }; >> >> + sdhc_2: mmc@8804000 { >> + compatible = "qcom,sm8750-sdhci", "qcom,sdhci-msm-v5"; >> + reg = <0 0x08804000 0 0x1000>; >> + >> + interrupts = , >> + ; >> + interrupt-names = "hc_irq", >> + "pwr_irq"; >> + >> + clocks = <&gcc GCC_SDCC2_AHB_CLK>, >> + <&gcc GCC_SDCC2_APPS_CLK>, >> + <&rpmhcc RPMH_CXO_CLK>; >> + clock-names = "iface", >> + "core", >> + "xo"; >> + >> + interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY >> + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; >> + interconnect-names = "sdhc-ddr", >> + "cpu-sdhc"; >> + >> + power-domains = <&rpmhpd RPMHPD_CX>; >> + operating-points-v2 = <&sdhc2_opp_table>; >> + >> + qcom,dll-config = <0x0007442c>; >> + qcom,ddr-config = <0x80040868>; >> + >> + iommus = <&apps_smmu 0x540 0x0>; >> + dma-coherent; >> + >> + bus-width = <4>; >> + max-sd-hs-hz = <37500000>; >> + >> + resets = <&gcc GCC_SDCC2_BCR>; >> + >> + status = "disabled"; >> + >> + sdhc2_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-100000000 { >> + opp-hz = /bits/ 64 <100000000>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-202000000 { >> + opp-hz = /bits/ 64 <202000000>; >> + required-opps = <&rpmhpd_opp_svs_l1>; >> + }; >> + }; >> + }; >> + >> cryptobam: dma-controller@1dc4000 { >> compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; >> reg = <0x0 0x01dc4000 0x0 0x28000>; >> @@ -3121,6 +3175,13 @@ data-pins { >> drive-strength = <2>; >> bias-pull-up; >> }; >> + >> + card-detect-pins { >> + pins = "gpio55"; >> + function = "gpio"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; > These are board specific, so move them to the board dts. Sure will update in V3. >> }; >> >> sdc2_default: sdc2-default-state { >> @@ -3141,6 +3202,13 @@ data-pins { >> drive-strength = <10>; >> bias-pull-up; >> }; >> + >> + card-detect-pins { >> + pins = "gpio55"; >> + function = "gpio"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; > Ditto. Sure will update in V3. Regards, Sarthak >> }; >> }; >> >> -- >> 2.34.1 >>