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([2600:8803:e7e4:1d00:55b7:b662:4c5b:a28e]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-336e5a2ab2esm1789178fac.17.2025.09.18.12.50.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 18 Sep 2025 12:50:46 -0700 (PDT) Message-ID: <62989891-e166-419b-b6ab-cf1eca781b32@baylibre.com> Date: Thu, 18 Sep 2025 14:50:45 -0500 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/8] Documentation: iio: ad4030: Add double PWM SPI offload doc To: Marcelo Schmitt , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: jic23@kernel.org, michael.hennerich@analog.com, nuno.sa@analog.com, eblanc@baylibre.com, andy@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, corbet@lwn.net, marcelo.schmitt1@gmail.com References: <4f3b1c516f8148e0b7e1c430bb184a2db12ade3c.1758214628.git.marcelo.schmitt@analog.com> Content-Language: en-US From: David Lechner In-Reply-To: <4f3b1c516f8148e0b7e1c430bb184a2db12ade3c.1758214628.git.marcelo.schmitt@analog.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Could use docs: instead of Documentation: in the subject to make it a bit shorter. Seems common enough. On 9/18/25 12:38 PM, Marcelo Schmitt wrote: > Document double PWM setup SPI offload wiring schema. > > Signed-off-by: Marcelo Schmitt > --- > Change log v1 -> v2 > - Swapped PWM numbering. > - Expanded double PWM description and capture zone description. > > Documentation/iio/ad4030.rst | 35 +++++++++++++++++++++++++++++++++++ > 1 file changed, 35 insertions(+) > > diff --git a/Documentation/iio/ad4030.rst b/Documentation/iio/ad4030.rst > index b57424b650a8..9501d3fee9bb 100644 > --- a/Documentation/iio/ad4030.rst > +++ b/Documentation/iio/ad4030.rst > @@ -92,6 +92,41 @@ Interleaved mode > In this mode, both channels conversion results are bit interleaved one SDO line. > As such the wiring is the same as `One lane mode`_. > > +SPI offload wiring > +^^^^^^^^^^^^^^^^^^ > + > +.. code-block:: > + > + +-------------+ +-------------+ > + | CNV |<-----+--| GPIO | > + | | +--| PWM0 | > + | | | | > + | | +--| PWM1 | > + | | | +-------------+ > + | | +->| TRIGGER | > + | CS |<--------| CS | > + | | | | > + | ADC | | SPI | > + | | | | > + | SDI |<--------| SDO | > + | SDO |-------->| SDI | > + | SCLK |<--------| SCLK | > + +-------------+ +-------------+ > + > +In this mode, both the ``cnv-gpios`` and a ``pwms`` properties are required. > +The ``pwms`` property specifies the PWM that is connected to the ADC CNV pin. > +The SPI offload will have a ``trigger-sources`` property to indicate the SPI > +offload (PWM) trigger source. For AD4030 and similar ADCs, there are two > +possible data transfer zones for sample N. One of them (zone 1) starts after the > +data conversion for sample N is complete while the other one (zone 2) starts 9.8 > +nanoseconds after the rising edge of CNV for sample N + 1. > + > +The configuration depicted in the above ASCII art is intended to perform data Could say "diagram" instead of "ASCII art" if you want to be more formal. > +transfer in zone 2. To achieve high sample rates while meeting ADC timing > +requirements, an offset is added between the rising edges of PWM0 and PWM1 to > +delay the SPI transfer until 9.8 nanoseconds after CNV rising edge. This > +requires a specialized PWM controller that can provide such an offset. > + Could add a link to the HDL project as an example of such hardware. > SPI Clock mode > -------------- > Good enough as it is. Reviewed-by: David Lechner