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Mon, 5 Oct 2026 12:31:02 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.14) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.2562.49 via Frontend Transport; Mon, 5 Oct 2026 12:31:02 -0700 From: Nicolin Chen To: CC: , , , , , , , , , , , Cristian Prundeanu , Breno Leitao Subject: [PATCH v11 03/11] iommu/arm-smmu-v3: Swap EVTQ_MSI_INDEX and GERROR_MSI_INDEX Date: Mon, 5 Oct 2026 12:30:46 -0700 Message-ID: <630e70ba13639e5bd86fca0b574dd47dddb7fb92.1791226953.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BY1PEPF0001AE1D:EE_|CH3PR12MB9146:EE_ X-MS-Office365-Filtering-Correlation-Id: 21ea8201-2555-4b37-d7ec-08df231740c5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|23010399003|376014|36860700016|1800799024|6133799003|18002099003|22082099003|10067099003|56012099006|11063799006|5023799004; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: duDkKLLiWZ9mhs3AfUyzUCAGIIKVxe4fj1ZUEl83dn/2dMleDG/EJaL4weRrZ/FVHs3xU49vc6RsHlUmpjNVmw1GH7HbMBbKQpA8wPL7UfqZc7t7kqd0G9GeEv89C1N1m019YiodWFxGrBDpeZPM5mvIGUNwByA+Ha9nEYgNQFVqySw/BiZh+2Dl5k/5i1h2885+CdIFs18O8b2coKkGCSavUYPKEgH55tzo0sbsofWr8cf9gypkfHaXFDdiCUybCMmwqHTUM9X1h0XrWPH/9CyRvtfjsCQMuFAmJnz5LpfRP+16FxI9ta+rnQW0lwVvYYcJK28j39d6qp5ASJfvFvXbkvyyUmHGWx43oPbtNUrk8zGURQTpHZJZjNlBgy7HLb+zCPGmFb6ptFBYYInV2aphwJ/7nSfZ/Si6SUYo3E+azdVNvgfuGfC2CkVgF3+L X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Oct 2026 19:31:28.7630 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 21ea8201-2555-4b37-d7ec-08df231740c5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BY1PEPF0001AE1D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9146 The nvec trick in arm_smmu_setup_msis() works well on PRIQ since its index is the last index in enum arm_smmu_msi_index, but it does not work well on the EVTQ as its index is 0. A subsequent change will make EVTQ optional so it can be disabled in kdump mode. This can skip its MSI vector allocation. The index is driver-internal to select arm_smmu_msi_cfg[] register set and the corresponding MSI slot. Nothing else. Swap EVTQ_MSI_INDEX and GERROR_MSI_INDEX. Then, arm_smmu_setup_msis() will simply decrease nvec when EVTQ is disabled. No functional change intended. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index aeace4335abfe..6ff61565f7583 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -57,8 +57,8 @@ static struct iommu_dirty_ops arm_smmu_dirty_ops; static DEFINE_STATIC_KEY_FALSE(arm_smmu_erratum_repeat_tlbi_cfgi_key); enum arm_smmu_msi_index { - EVTQ_MSI_INDEX, GERROR_MSI_INDEX, + EVTQ_MSI_INDEX, PRIQ_MSI_INDEX, ARM_SMMU_MAX_MSIS, }; @@ -68,16 +68,16 @@ static_assert(sizeof(struct arm_smmu_ste) == NUM_ENTRY_QWORDS * sizeof(u64)); static_assert(sizeof(struct arm_smmu_cd) == NUM_ENTRY_QWORDS * sizeof(u64)); static phys_addr_t arm_smmu_msi_cfg[ARM_SMMU_MAX_MSIS][3] = { - [EVTQ_MSI_INDEX] = { - ARM_SMMU_EVTQ_IRQ_CFG0, - ARM_SMMU_EVTQ_IRQ_CFG1, - ARM_SMMU_EVTQ_IRQ_CFG2, - }, [GERROR_MSI_INDEX] = { ARM_SMMU_GERROR_IRQ_CFG0, ARM_SMMU_GERROR_IRQ_CFG1, ARM_SMMU_GERROR_IRQ_CFG2, }, + [EVTQ_MSI_INDEX] = { + ARM_SMMU_EVTQ_IRQ_CFG0, + ARM_SMMU_EVTQ_IRQ_CFG1, + ARM_SMMU_EVTQ_IRQ_CFG2, + }, [PRIQ_MSI_INDEX] = { ARM_SMMU_PRIQ_IRQ_CFG0, ARM_SMMU_PRIQ_IRQ_CFG1, @@ -4965,15 +4965,15 @@ static void arm_smmu_setup_msis(struct arm_smmu_device *smmu) return; } - /* Allocate MSIs for evtq, gerror and priq. Ignore cmdq */ + /* Allocate MSIs for gerror, evtq and priq. Ignore cmdq */ ret = platform_device_msi_init_and_alloc_irqs(dev, nvec, arm_smmu_write_msi_msg); if (ret) { dev_warn(dev, "failed to allocate MSIs - falling back to wired irqs\n"); return; } - smmu->evtq.q.irq = msi_get_virq(dev, EVTQ_MSI_INDEX); smmu->gerr_irq = msi_get_virq(dev, GERROR_MSI_INDEX); + smmu->evtq.q.irq = msi_get_virq(dev, EVTQ_MSI_INDEX); smmu->priq.q.irq = msi_get_virq(dev, PRIQ_MSI_INDEX); /* Add callback to free MSIs on teardown */ -- 2.43.0