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Thu, 05 Jun 2025 03:33:22 -0700 (PDT) Message-ID: <632eadac-e5fd-4e50-9ced-cd4f2b9e6c82@linaro.org> Date: Thu, 5 Jun 2025 11:33:21 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 06/11] KVM: arm64: Add trap configs for PMSDSFR_EL1 To: Marc Zyngier Cc: Catalin Marinas , Will Deacon , Mark Rutland , Jonathan Corbet , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev References: <20250529-james-perf-feat_spe_eft-v2-0-a01a9baad06a@linaro.org> <20250529-james-perf-feat_spe_eft-v2-6-a01a9baad06a@linaro.org> <867c1ze4pg.wl-maz@kernel.org> <2fb1965b-bef9-4a8e-a1c7-c8a77d957b23@linaro.org> <87a56ned6r.wl-maz@kernel.org> Content-Language: en-US From: James Clark In-Reply-To: <87a56ned6r.wl-maz@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 04/06/2025 4:31 pm, Marc Zyngier wrote: > On Tue, 03 Jun 2025 10:50:23 +0100, > James Clark wrote: >> >> >> >> On 29/05/2025 5:56 pm, Marc Zyngier wrote: >>> On Thu, 29 May 2025 12:30:27 +0100, >>> James Clark wrote: >>>> >>>> SPE data source filtering (SPE_FEAT_FDS) adds a new register >>>> PMSDSFR_EL1, add the trap configs for it. >>>> >>>> Signed-off-by: James Clark >>>> --- >>>> arch/arm64/kvm/emulate-nested.c | 1 + >>>> arch/arm64/kvm/sys_regs.c | 1 + >>>> 2 files changed, 2 insertions(+) >>>> >>>> diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c >>>> index 0fcfcc0478f9..05d3e6b93ae9 100644 >>>> --- a/arch/arm64/kvm/emulate-nested.c >>>> +++ b/arch/arm64/kvm/emulate-nested.c >>>> @@ -1169,6 +1169,7 @@ static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = { >>>> SR_TRAP(SYS_PMSIRR_EL1, CGT_MDCR_TPMS), >>>> SR_TRAP(SYS_PMSLATFR_EL1, CGT_MDCR_TPMS), >>>> SR_TRAP(SYS_PMSNEVFR_EL1, CGT_MDCR_TPMS), >>>> + SR_TRAP(SYS_PMSDSFR_EL1, CGT_MDCR_TPMS), >>>> SR_TRAP(SYS_TRFCR_EL1, CGT_MDCR_TTRF), >>>> SR_TRAP(SYS_TRBBASER_EL1, CGT_MDCR_E2TB), >>>> SR_TRAP(SYS_TRBLIMITR_EL1, CGT_MDCR_E2TB), >>>> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c >>>> index 5dde9285afc8..9f544ac7b5a6 100644 >>>> --- a/arch/arm64/kvm/sys_regs.c >>>> +++ b/arch/arm64/kvm/sys_regs.c >>>> @@ -2956,6 +2956,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { >>>> { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access }, >>>> { SYS_DESC(SYS_PMBPTR_EL1), undef_access }, >>>> { SYS_DESC(SYS_PMBSR_EL1), undef_access }, >>>> + { SYS_DESC(SYS_PMSDSFR_EL1), undef_access }, >>> >>> PMSDSFR_EL1 has an offset in the VNCR page (0x858), and must be >>> described as such. This is equally true for a bunch of other >>> SPE-related registers, so you might as well fix those while you're at >>> it. >>> >>> Thanks, >>> >>> M. >>> >> >> I got a bit stuck with what that would look like with registers that >> are only undef in case there was something that I missed, but do I >> just document the offsets? >> >> +++ b/arch/arm64/include/asm/vncr_mapping.h >> @@ -87,6 +87,8 @@ >> #define VNCR_PMSICR_EL1 0x838 >> #define VNCR_PMSIRR_EL1 0x840 >> #define VNCR_PMSLATFR_EL1 0x848 >> +#define VNCR_PMSNEVFR_EL1 0x850 >> +#define VNCR_PMSDSFR_EL1 0x858 >> > > This should be enough. > Thanks, I'll resend with these added. >> +++ b/arch/arm64/include/asm/kvm_host.h >> @@ -596,6 +596,16 @@ enum vcpu_sysreg { >> VNCR(ICH_HCR_EL2), >> VNCR(ICH_VMCR_EL2), >> >> + /* SPE Registers */ >> + VNCR(PMBLIMITR_EL1), >> + VNCR(PMBPTR_EL1), >> + VNCR(PMBSR_EL1), >> + VNCR(PMSCR_EL1), >> + VNCR(PMSEVFR_EL1), >> + VNCR(PMSICR_EL1), >> + VNCR(PMSIRR_EL1), >> + VNCR(PMSLATFR_EL1), > > I don't see a point in having those until we actually have SPE support > for guests, if ever, as these will potentially increase the size of > the vcpu sysreg array for no good reason. > >> And then sys_reg_descs[] remain as "{ SYS_DESC(SYS_PMBLIMITR_EL1), >> undef_access }," rather than EL2_REG_VNCR() because we don't actually >> want to change to bad_vncr_trap()? > > This seem OK for now. We may want to refine this in the future though, > as these registers cannot trap when NV is enabled. Yes, this is a bug > in the architecture. > >> There are some other parts about fine grained traps and res0 bits for >> NV, but they all already look to be setup correctly. Except >> HDFGRTR2_EL2.nPMSDSFR_EL1, but it's inverted, none of the FGT2 traps >> are configured currently and PMSDSFR_EL1 is already trapped by >> MDCR_EL2 anyway. > > Can you elaborate on that? We have: > > SR_FGT(SYS_PMSDSFR_EL1, HDFGRTR2, nPMSDSFR_EL1, 0), > > which seems to match the spec. > > We also have full support for FEAT_FGT2 already (even if we have no > support for the stuff they trap). Oh I think that was misleading, the version I was poking around on didn't have the FEAT_FGT2 stuff applied yet but I see it now. And yes, as you say, what's there matches the spec. > > Thanks, > > M. >