From: Andrew Lunn <andrew@lunn.ch>
To: "Grégoire Layet" <gregoire.layet@9elements.com>
Cc: joel@jms.id.au, andrew@codeconstruct.com.au,
jacky_chou@aspeedtech.com, yh_chung@aspeedtech.com,
ninad@linux.ibm.com, linux-aspeed@lists.ozlabs.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 0/2] soc: aspeed: Add BMC and host driver for PCIe BMC device
Date: Mon, 8 Jun 2026 20:05:17 +0200 [thread overview]
Message-ID: <63654bb5-c246-41c4-bb7e-5bfa23e59f2e@lunn.ch> (raw)
In-Reply-To: <cover.1780929570.git.gregoire.layet@9elements.com>
On Mon, Jun 08, 2026 at 02:51:21PM +0000, Grégoire Layet wrote:
> This is a v2 for upstreaming the VUART over PCIe BMC device driver from the ASPEED kernel SDK (branch master-v6.18) [1].
> There are two drivers: a BMC-side driver and a host-side driver.
> Together they enable host<->BMC VUART communication via PCIe.
I would like to see somewhere a comment about security. From the
replies i got the host can access anything on the LPC bus of the
aspeed. What are the implications of that? What are typically on such
a bus? TPMs are often there, but does a BMC have a TPM?
Andrew
next prev parent reply other threads:[~2026-06-08 18:05 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-02 14:42 [PATCH v1 " Grégoire Layet
2026-06-02 14:42 ` [PATCH v1 1/2] soc: aspeed: add BMC-side PCIe BMC device driver Grégoire Layet
2026-06-02 14:42 ` [PATCH v1 2/2] soc: aspeed: add host-side " Grégoire Layet
2026-06-02 15:49 ` Andrew Lunn
2026-06-03 13:43 ` Grégoire Layet
2026-06-03 14:30 ` Andrew Lunn
2026-06-04 0:44 ` Andrew Jeffery
2026-06-04 0:46 ` Andrew Jeffery
2026-06-08 14:51 ` [PATCH v2 0/2] soc: aspeed: Add BMC and host driver for PCIe BMC device Grégoire Layet
2026-06-08 14:51 ` [PATCH v2 1/2] soc: aspeed: add BMC-side PCIe BMC device driver Grégoire Layet
2026-06-10 12:33 ` Andrew Jeffery
2026-06-11 8:40 ` Grégoire Layet
2026-06-12 9:21 ` Grégoire Layet
2026-06-16 0:16 ` Andrew Jeffery
2026-06-17 6:40 ` Grégoire Layet
2026-06-18 0:58 ` Andrew Jeffery
2026-06-08 14:51 ` [PATCH v2 2/2] soc: aspeed: add host-side " Grégoire Layet
2026-06-10 12:51 ` Andrew Jeffery
2026-06-11 8:41 ` Grégoire Layet
2026-06-08 18:05 ` Andrew Lunn [this message]
2026-06-09 13:34 ` [PATCH v2 0/2] soc: aspeed: Add BMC and host driver for PCIe BMC device Grégoire Layet
2026-06-23 14:25 ` [PATCH v3 0/7] " Grégoire Layet
2026-06-23 14:25 ` [PATCH v3 1/7] dt-bindings: serial: 8250: aspeed: add compatible string for ast2600 Grégoire Layet
2026-06-24 7:15 ` Krzysztof Kozlowski
2026-06-24 12:48 ` Grégoire Layet
2026-06-23 14:25 ` [PATCH v3 2/7] dt-bindings: serial: 8250: aspeed: add aspeed,vuart-over-pci bool prop Grégoire Layet
2026-06-24 7:17 ` Krzysztof Kozlowski
2026-06-24 12:48 ` Grégoire Layet
2026-06-25 6:36 ` Krzysztof Kozlowski
2026-06-25 9:10 ` Grégoire Layet
2026-06-23 14:25 ` [PATCH v3 3/7] serial: 8250_aspeed_vuart: add aspeed,ast2600-vuart compatible string Grégoire Layet
2026-06-23 14:25 ` [PATCH v3 4/7] serial: 8250_aspeed_vuart: add VUART over PCI Grégoire Layet
2026-06-23 14:25 ` [PATCH v3 5/7] soc: aspeed: add host-side PCIe BMC device driver Grégoire Layet
2026-06-23 14:25 ` [PATCH v3 6/7] ARM: dts: aspeed: g6: Change vuart compatible string for ast2600 Grégoire Layet
2026-06-24 7:19 ` Krzysztof Kozlowski
2026-06-24 13:44 ` Grégoire Layet
2026-06-23 14:25 ` [PATCH v3 7/7] ARM: dts: aspeed: g6: add aspeed,vuart-over-pci prop to vuart3 and 4 Grégoire Layet
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