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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa20e046c68sm210747166b.167.2024.11.15.12.26.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 15 Nov 2024 12:26:06 -0800 (PST) Message-ID: <636c2392-bcd6-45ae-a7f7-ed893479d3dd@oss.qualcomm.com> Date: Fri, 15 Nov 2024 21:26:03 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/6] arm64: dts: qcom: Add base SM8750 dtsi To: Melody Olvera , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Geert Uytterhoeven , Dmitry Baryshkov , Neil Armstrong , Arnd Bergmann , =?UTF-8?Q?N=C3=ADcolas_F_=2E_R_=2E_A_=2E_Prado?= , Trilok Soni , Satya Durga Srinivasu Prabhala Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Taniya Das , Jishnu Prakash , Raviteja Laggyshetty References: <20241112004936.2810509-1-quic_molvera@quicinc.com> <20241112004936.2810509-4-quic_molvera@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20241112004936.2810509-4-quic_molvera@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: ktzEQZjiLvRasGRmyoh9VxeYgYBVqsbR X-Proofpoint-GUID: ktzEQZjiLvRasGRmyoh9VxeYgYBVqsbR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 impostorscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 malwarescore=0 spamscore=0 clxscore=1015 mlxscore=0 mlxlogscore=714 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411150171 On 12.11.2024 1:49 AM, Melody Olvera wrote: > Add the base dtsi for the SM8750 SoC describing the CPUs, GCC and > RPMHCC clock controllers, geni UART, interrupt controller, TLMM, > reserved memory, interconnects, and SMMU. > > Co-developed-by: Taniya Das > Signed-off-by: Taniya Das > Co-developed-by: Jishnu Prakash > Signed-off-by: Jishnu Prakash > Co-developed-by: Raviteja Laggyshetty > Signed-off-by: Raviteja Laggyshetty > Signed-off-by: Melody Olvera > --- [...] > + power-domain-names = "psci"; > + cpu-idle-states = <&cluster0_c4>; So here and on x1 we use cpu-idle-states instead of putting the idle state under domain-idle-states in CPU_PDn like on other PSCI OSI mode-supporting SoCs. IIUC it works out to be the same thing, but maybe we should stick to the latter for consistency [...] > + > + gic_its: msi-controller@16040000 { > + compatible = "arm,gic-v3-its"; > + reg = <0x0 0x16040000 0x0 0x20000>; > + > + msi-controller; > + #msi-cells = <1>; > + > + status = "disabled"; > + }; Any reason it's disabled? LGTM otherwise Konrad