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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abbad297430sm867677566b.5.2025.02.21.11.51.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 21 Feb 2025 11:51:22 -0800 (PST) Message-ID: <638f05f4-3a0e-459d-aec0-b925ca7f657c@oss.qualcomm.com> Date: Fri, 21 Feb 2025 20:51:19 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] arm64: dts: qcom: sm8750: Fix cluster hierarchy for idle states To: Maulik Shah , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jishnu Prakash , Raviteja Laggyshetty , Taniya Das , Melody Olvera Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, quic_lsrao@quicinc.com References: <20250218-sm8750_cluster_idle-v1-1-5529df00f642@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250218-sm8750_cluster_idle-v1-1-5529df00f642@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: h5icwm_2-b4Nzh4LxZo-zqCFDkN8l6r3 X-Proofpoint-ORIG-GUID: h5icwm_2-b4Nzh4LxZo-zqCFDkN8l6r3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-21_07,2025-02-20_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 adultscore=0 malwarescore=0 mlxscore=0 priorityscore=1501 lowpriorityscore=0 mlxlogscore=865 suspectscore=0 phishscore=0 spamscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2502210135 On 18.02.2025 7:58 AM, Maulik Shah wrote: > SM8750 have two different clusters. cluster0 have CPU 0-5 as child and > cluster1 have CPU 6-7 as child. Each cluster requires its own idle state > and power domain in order to achieve complete domain sleep state. > > However only single cluster idle state is added mapping CPU 0-7 to the > same power domain. Fix this by correctly mapping each CPU to respective > cluster power domain and add domain idle state for cluster1. > > Fixes: 068c3d3c83be ("arm64: dts: qcom: Add base SM8750 dtsi") > Signed-off-by: Maulik Shah > --- > arch/arm64/boot/dts/qcom/sm8750.dtsi | 36 +++++++++++++++++++++++++----------- > 1 file changed, 25 insertions(+), 11 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi > index 3bbd7d18598ee0a3a0d5130c03a3166e1fc14d82..3af928be5b68b47988dd55f4add8e3712f07d5ab 100644 > --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi > @@ -178,7 +178,15 @@ cluster1_c4: cpu-sleep-1 { > }; > > domain-idle-states { > - cluster_cl5: cluster-sleep-0 { > + cluster0_cl5: cluster-sleep-0 { > + compatible = "domain-idle-state"; > + arm,psci-suspend-param = <0x01000054>; > + entry-latency-us = <2150>; > + exit-latency-us = <1983>; > + min-residency-us = <9144>; > + }; I don't think this is necessary, you should be gtg with just creating the new power domain for cluster 0/1 and pointing both to the same cluster idle state (unless they both need different latency numbers Konrad