From: James Clark <james.clark@arm.com>
To: Ian Rogers <irogers@google.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>,
Kan Liang <kan.liang@linux.intel.com>,
Ahmad Yasin <ahmad.yasin@intel.com>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Stephane Eranian <eranian@google.com>,
Andi Kleen <ak@linux.intel.com>,
Perry Taylor <perry.taylor@intel.com>,
Samantha Alt <samantha.alt@intel.com>,
Caleb Biggers <caleb.biggers@intel.com>,
Weilin Wang <weilin.wang@intel.com>,
Edward Baker <edward.baker@intel.com>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>, Namhyung Kim <namhyung@kernel.org>,
Adrian Hunter <adrian.hunter@intel.com>,
Florian Fischer <florian.fischer@muhq.space>,
Rob Herring <robh@kernel.org>,
Zhengjun Xing <zhengjun.xing@linux.intel.com>,
John Garry <john.g.garry@oracle.com>,
Kajol Jain <kjain@linux.ibm.com>,
Sumanth Korikkar <sumanthk@linux.ibm.com>,
Thomas Richter <tmricht@linux.ibm.com>,
Tiezhu Yang <yangtiezhu@loongson.cn>,
Ravi Bangoria <ravi.bangoria@amd.com>,
Leo Yan <leo.yan@linaro.org>,
Yang Jihong <yangjihong1@huawei.com>,
Suzuki Poulouse <suzuki.poulose@arm.com>,
Kang Minchul <tegongkang@gmail.com>,
Athira Rajeev <atrajeev@linux.vnet.ibm.com>,
linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1 21/40] perf parse-events: Wildcard legacy cache events
Date: Wed, 26 Apr 2023 11:11:39 +0100 [thread overview]
Message-ID: <6396e5dc-bf53-ce0d-15ea-0a1aedecf691@arm.com> (raw)
In-Reply-To: <20230426070050.1315519-22-irogers@google.com>
On 26/04/2023 08:00, Ian Rogers wrote:
> It is inconsistent that "perf stat -e instructions-retired" wildcard
> opens on all PMUs while legacy cache events like "perf stat -e
> L1-dcache-load-miss" do not. A behavior introduced by hybrid is that a
> legacy cache event like L1-dcache-load-miss should wildcard open on
> all hybrid PMUs. A call to is_event_supported is necessary for each
> PMU, a failure of which results in the event not being added. Rather
> than special case that logic, move it into the main legacy cache event
> case and attempt to open legacy cache events on all PMUs.
>
> Signed-off-by: Ian Rogers <irogers@google.com>
> ---
> tools/perf/util/parse-events-hybrid.c | 33 -------------
> tools/perf/util/parse-events-hybrid.h | 7 ---
> tools/perf/util/parse-events.c | 70 ++++++++++++++-------------
> tools/perf/util/parse-events.h | 3 +-
> tools/perf/util/parse-events.y | 2 +-
> 5 files changed, 39 insertions(+), 76 deletions(-)
>
> diff --git a/tools/perf/util/parse-events-hybrid.c b/tools/perf/util/parse-events-hybrid.c
> index 7c9f9150bad5..d2c0be051d46 100644
> --- a/tools/perf/util/parse-events-hybrid.c
> +++ b/tools/perf/util/parse-events-hybrid.c
> @@ -179,36 +179,3 @@ int parse_events__add_numeric_hybrid(struct parse_events_state *parse_state,
> return add_raw_hybrid(parse_state, list, attr, name, metric_id,
> config_terms);
> }
> -
> -int parse_events__add_cache_hybrid(struct list_head *list, int *idx,
> - struct perf_event_attr *attr,
> - const char *name,
> - const char *metric_id,
> - struct list_head *config_terms,
> - bool *hybrid,
> - struct parse_events_state *parse_state)
> -{
> - struct perf_pmu *pmu;
> - int ret;
> -
> - *hybrid = false;
> - if (!perf_pmu__has_hybrid())
> - return 0;
> -
> - *hybrid = true;
> - perf_pmu__for_each_hybrid_pmu(pmu) {
> - LIST_HEAD(terms);
> -
> - if (pmu_cmp(parse_state, pmu))
> - continue;
> -
> - copy_config_terms(&terms, config_terms);
> - ret = create_event_hybrid(PERF_TYPE_HW_CACHE, idx, list,
> - attr, name, metric_id, &terms, pmu);
> - free_config_terms(&terms);
> - if (ret)
> - return ret;
> - }
> -
> - return 0;
> -}
> diff --git a/tools/perf/util/parse-events-hybrid.h b/tools/perf/util/parse-events-hybrid.h
> index cbc05fec02a2..bc2966e73897 100644
> --- a/tools/perf/util/parse-events-hybrid.h
> +++ b/tools/perf/util/parse-events-hybrid.h
> @@ -15,11 +15,4 @@ int parse_events__add_numeric_hybrid(struct parse_events_state *parse_state,
> struct list_head *config_terms,
> bool *hybrid);
>
> -int parse_events__add_cache_hybrid(struct list_head *list, int *idx,
> - struct perf_event_attr *attr,
> - const char *name, const char *metric_id,
> - struct list_head *config_terms,
> - bool *hybrid,
> - struct parse_events_state *parse_state);
> -
> #endif /* __PERF_PARSE_EVENTS_HYBRID_H */
> diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c
> index 9b2d7b6572c2..e007b2bc1ab4 100644
> --- a/tools/perf/util/parse-events.c
> +++ b/tools/perf/util/parse-events.c
> @@ -471,46 +471,50 @@ static int parse_events__decode_legacy_cache(const char *name, int pmu_type, __u
>
> int parse_events_add_cache(struct list_head *list, int *idx, const char *name,
> struct parse_events_error *err,
> - struct list_head *head_config,
> - struct parse_events_state *parse_state)
> + struct list_head *head_config)
> {
> - struct perf_event_attr attr;
> - LIST_HEAD(config_terms);
> - const char *config_name, *metric_id;
> - int ret;
> - bool hybrid;
> + struct perf_pmu *pmu = NULL;
> + bool found_supported = false;
> + const char *config_name = get_config_name(head_config);
> + const char *metric_id = get_config_metric_id(head_config);
>
> + while ((pmu = perf_pmu__scan(pmu)) != NULL) {
> + LIST_HEAD(config_terms);
> + struct perf_event_attr attr;
> + int ret;
>
> - memset(&attr, 0, sizeof(attr));
> - attr.type = PERF_TYPE_HW_CACHE;
> - ret = parse_events__decode_legacy_cache(name, /*pmu_type=*/0, &attr.config);
> - if (ret)
> - return ret;
> + /*
> + * Skip uncore PMUs for performance. Software PMUs can open
> + * PERF_TYPE_HW_CACHE, so skip.
> + */
> + if (pmu->is_uncore || pmu->type == PERF_TYPE_SOFTWARE)
> + continue;
>
> - if (head_config) {
> - if (config_attr(&attr, head_config, err,
> - config_term_common))
> - return -EINVAL;
> + memset(&attr, 0, sizeof(attr));
> + attr.type = PERF_TYPE_HW_CACHE;
>
> - if (get_config_terms(head_config, &config_terms))
> - return -ENOMEM;
> - }
> + ret = parse_events__decode_legacy_cache(name, pmu->type, &attr.config);
> + if (ret)
> + return ret;
>
> - config_name = get_config_name(head_config);
> - metric_id = get_config_metric_id(head_config);
> - ret = parse_events__add_cache_hybrid(list, idx, &attr,
> - config_name ? : name,
> - metric_id,
> - &config_terms,
> - &hybrid, parse_state);
> - if (hybrid)
> - goto out_free_terms;
> + if (!is_event_supported(PERF_TYPE_HW_CACHE, attr.config))
> + continue;
Hi Ian,
I get a test failure on Arm from this commit. I think it's related to
this check for support that's failing but I'm not sure what the
resolution should be. I also couldn't see why the metrics in
test_soc/cpu/metrics.json aren't run on x86 (assuming they're generic
'test anywhere' type metrics?).
$ perf test -vvv "parsing of PMU event table metrics with fake"
...
parsing 'dcache_miss_cpi': 'l1d\-loads\-misses / inst_retired.any'
parsing metric: l1d\-loads\-misses / inst_retired.any
Attempting to add event pmu 'inst_retired.any' with
'inst_retired.any,' that may result in non-fatal errors
After aliases, add event pmu 'inst_retired.any' with
'inst_retired.any,' that may result in non-fatal errors
inst_retired.any -> fake_pmu/inst_retired.any/
------------------------------------------------------------
perf_event_attr:
type 3
config 0x800010000
disabled 1
------------------------------------------------------------
sys_perf_event_open: pid 0 cpu -1 group_fd -1 flags 0x8
sys_perf_event_open failed, error -2
check_parse_fake failed
test child finished with -1
---- end ----
PMU events subtest 4: FAILED!
>
> - ret = add_event(list, idx, &attr, config_name ? : name, metric_id,
> - &config_terms);
> -out_free_terms:
> - free_config_terms(&config_terms);
> - return ret;
> + found_supported = true;
> +
> + if (head_config) {
> + if (config_attr(&attr, head_config, err,
> + config_term_common))
> + return -EINVAL;
> +
> + if (get_config_terms(head_config, &config_terms))
> + return -ENOMEM;
> + }
> +
> + ret = add_event(list, idx, &attr, config_name ? : name, metric_id, &config_terms);
> + free_config_terms(&config_terms);
> + }
> + return found_supported ? 0: -EINVAL;
> }
>
> #ifdef HAVE_LIBTRACEEVENT
> diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h
> index 5acb62c2e00a..0c26303f7f63 100644
> --- a/tools/perf/util/parse-events.h
> +++ b/tools/perf/util/parse-events.h
> @@ -172,8 +172,7 @@ int parse_events_add_tool(struct parse_events_state *parse_state,
> int tool_event);
> int parse_events_add_cache(struct list_head *list, int *idx, const char *name,
> struct parse_events_error *error,
> - struct list_head *head_config,
> - struct parse_events_state *parse_state);
> + struct list_head *head_config);
> int parse_events_add_breakpoint(struct list_head *list, int *idx,
> u64 addr, char *type, u64 len);
> int parse_events_add_pmu(struct parse_events_state *parse_state,
> diff --git a/tools/perf/util/parse-events.y b/tools/perf/util/parse-events.y
> index f84fa1b132b3..cc7528558845 100644
> --- a/tools/perf/util/parse-events.y
> +++ b/tools/perf/util/parse-events.y
> @@ -476,7 +476,7 @@ PE_LEGACY_CACHE opt_event_config
>
> list = alloc_list();
> ABORT_ON(!list);
> - err = parse_events_add_cache(list, &parse_state->idx, $1, error, $2, parse_state);
> + err = parse_events_add_cache(list, &parse_state->idx, $1, error, $2);
>
> parse_events_terms__delete($2);
> free($1);
next prev parent reply other threads:[~2023-04-26 10:12 UTC|newest]
Thread overview: 71+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-26 7:00 [PATCH v1 00/40] Fix perf on Intel hybrid CPUs Ian Rogers
2023-04-26 7:00 ` [PATCH v1 01/40] perf stat: Introduce skippable evsels Ian Rogers
2023-04-26 23:26 ` Yasin, Ahmad
2023-04-27 0:37 ` Ian Rogers
2023-04-27 2:03 ` Ian Rogers
2023-04-27 18:52 ` Liang, Kan
2023-04-27 20:21 ` Ian Rogers
2023-04-27 21:00 ` Namhyung Kim
2023-04-27 21:09 ` Ian Rogers
2023-04-26 7:00 ` [PATCH v1 02/40] perf vendor events intel: Add alderlake metric constraints Ian Rogers
2023-04-26 7:00 ` [PATCH v1 03/40] perf vendor events intel: Add icelake " Ian Rogers
2023-04-27 19:06 ` Liang, Kan
2023-04-27 20:22 ` Ian Rogers
2023-04-26 7:00 ` [PATCH v1 04/40] perf vendor events intel: Add icelakex " Ian Rogers
2023-04-26 7:00 ` [PATCH v1 05/40] perf vendor events intel: Add sapphirerapids " Ian Rogers
2023-04-26 7:00 ` [PATCH v1 06/40] perf vendor events intel: Add tigerlake " Ian Rogers
2023-04-26 7:00 ` [PATCH v1 07/40] perf stat: Avoid segv on counter->name Ian Rogers
2023-04-27 19:11 ` Liang, Kan
2023-04-27 19:34 ` Arnaldo Carvalho de Melo
2023-04-26 7:00 ` [PATCH v1 08/40] perf test: Test more sysfs events Ian Rogers
2023-04-27 19:38 ` Liang, Kan
2023-04-27 20:23 ` Ian Rogers
2023-04-26 7:00 ` [PATCH v1 09/40] perf test: Use valid for PMU tests Ian Rogers
2023-04-27 19:39 ` Liang, Kan
2023-04-26 7:00 ` [PATCH v1 10/40] perf test: Mask config then test Ian Rogers
2023-04-27 19:39 ` Liang, Kan
2023-04-26 7:00 ` [PATCH v1 11/40] perf test: Test more with config_cache Ian Rogers
2023-04-27 19:40 ` Liang, Kan
2023-04-26 7:00 ` [PATCH v1 12/40] perf test: Roundtrip name, don't assume 1 event per name Ian Rogers
2023-04-27 19:44 ` Liang, Kan
2023-04-26 7:00 ` [PATCH v1 13/40] perf parse-events: Set attr.type to PMU type early Ian Rogers
2023-04-27 20:00 ` Liang, Kan
2023-04-26 7:00 ` [PATCH v1 14/40] perf print-events: Avoid unnecessary strlist Ian Rogers
2023-04-27 20:01 ` Liang, Kan
2023-04-26 7:00 ` [PATCH v1 15/40] perf parse-events: Avoid scanning PMUs before parsing Ian Rogers
2023-04-27 20:06 ` Liang, Kan
2023-04-26 7:00 ` [PATCH v1 16/40] perf test: Validate events with hyphens in Ian Rogers
2023-04-27 20:08 ` Liang, Kan
2023-04-26 7:00 ` [PATCH v1 17/40] perf evsel: Modify group pmu name for software events Ian Rogers
2023-04-27 20:12 ` Liang, Kan
2023-04-26 7:00 ` [PATCH v1 18/40] perf test: Move x86 hybrid tests to arch/x86 Ian Rogers
2023-04-27 21:42 ` Liang, Kan
2023-04-26 7:00 ` [PATCH v1 19/40] perf test x86 hybrid: Don't assume evlist order Ian Rogers
2023-04-26 7:00 ` [PATCH v1 20/40] perf parse-events: Support PMUs for legacy cache events Ian Rogers
2023-04-26 7:00 ` [PATCH v1 21/40] perf parse-events: Wildcard " Ian Rogers
2023-04-26 10:11 ` James Clark [this message]
2023-04-27 5:50 ` Ian Rogers
2023-04-27 21:02 ` Ian Rogers
2023-04-26 7:00 ` [PATCH v1 22/40] perf print-events: Print legacy cache events for each PMU Ian Rogers
2023-04-26 7:00 ` [PATCH v1 23/40] perf parse-events: Support wildcards on raw events Ian Rogers
2023-04-26 7:00 ` [PATCH v1 24/40] perf parse-events: Remove now unused hybrid logic Ian Rogers
2023-04-26 7:00 ` [PATCH v1 25/40] perf parse-events: Minor type safety cleanup Ian Rogers
2023-04-26 7:00 ` [PATCH v1 26/40] perf parse-events: Add pmu filter Ian Rogers
2023-04-26 7:00 ` [PATCH v1 27/40] perf stat: Make cputype filter generic Ian Rogers
2023-04-26 7:00 ` [PATCH v1 28/40] perf test: Add cputype testing to perf stat Ian Rogers
2023-04-26 7:00 ` [PATCH v1 29/40] perf test: Fix parse-events tests for >1 core PMU Ian Rogers
2023-04-26 7:00 ` [PATCH v1 30/40] perf parse-events: Support hardware events as terms Ian Rogers
2023-04-26 7:00 ` [PATCH v1 31/40] perf parse-events: Avoid error when assigning a term Ian Rogers
2023-04-26 7:00 ` [PATCH v1 32/40] perf parse-events: Avoid error when assigning a legacy cache term Ian Rogers
2023-04-26 7:00 ` [PATCH v1 33/40] perf parse-events: Don't auto merge hybrid wildcard events Ian Rogers
2023-04-26 7:00 ` [PATCH v1 34/40] perf parse-events: Don't reorder atom cpu events Ian Rogers
2023-04-26 7:00 ` [PATCH v1 35/40] perf metrics: Be PMU specific for referenced metrics Ian Rogers
2023-04-26 7:00 ` [PATCH v1 36/40] perf metric: Json flag to not group events if gathering a metric group Ian Rogers
2023-04-26 7:00 ` [PATCH v1 37/40] perf stat: Command line PMU metric filtering Ian Rogers
2023-04-26 7:00 ` [PATCH v1 38/40] perf vendor events intel: Correct alderlake metrics Ian Rogers
2023-04-26 7:00 ` [PATCH v1 39/40] perf jevents: Don't rewrite metrics across PMUs Ian Rogers
2023-04-26 7:00 ` [PATCH v1 40/40] perf metrics: Be PMU specific in event match Ian Rogers
2023-04-26 13:53 ` [PATCH v1 00/40] Fix perf on Intel hybrid CPUs Liang, Kan
2023-04-26 21:09 ` Arnaldo Carvalho de Melo
2023-04-26 21:33 ` Arnaldo Carvalho de Melo
2023-04-26 22:07 ` Liang, Kan
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=6396e5dc-bf53-ce0d-15ea-0a1aedecf691@arm.com \
--to=james.clark@arm.com \
--cc=acme@kernel.org \
--cc=adrian.hunter@intel.com \
--cc=ahmad.yasin@intel.com \
--cc=ak@linux.intel.com \
--cc=alexander.shishkin@linux.intel.com \
--cc=atrajeev@linux.vnet.ibm.com \
--cc=caleb.biggers@intel.com \
--cc=edward.baker@intel.com \
--cc=eranian@google.com \
--cc=florian.fischer@muhq.space \
--cc=irogers@google.com \
--cc=john.g.garry@oracle.com \
--cc=jolsa@kernel.org \
--cc=kan.liang@linux.intel.com \
--cc=kjain@linux.ibm.com \
--cc=leo.yan@linaro.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-perf-users@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=mingo@redhat.com \
--cc=namhyung@kernel.org \
--cc=perry.taylor@intel.com \
--cc=peterz@infradead.org \
--cc=ravi.bangoria@amd.com \
--cc=robh@kernel.org \
--cc=samantha.alt@intel.com \
--cc=sumanthk@linux.ibm.com \
--cc=suzuki.poulose@arm.com \
--cc=tegongkang@gmail.com \
--cc=tmricht@linux.ibm.com \
--cc=weilin.wang@intel.com \
--cc=yangjihong1@huawei.com \
--cc=yangtiezhu@loongson.cn \
--cc=zhengjun.xing@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®