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>>> >>> /* >>> - * CXL Memory Devices must have the 502h class code set (CXL >>> - * 3.0, 8.1.12.1). >>> + * CXL Memory Devices must have the 502h class code set >>> + * (CXL 3.2, 8.1.12.1). >>> */ >>> - if ((dev->class >> 8) != PCI_CLASS_MEMORY_CXL) >>> + if (FIELD_GET(PCI_CLASS_CODE_MASK, dev->class) != PCI_CLASS_MEMORY_CXL) >>> return false; > Hm, this doesn't look more readable TBH. > > Refactoring changes like this one should be submitted separately from > this patch set. If any of them are controversial, they delay upstreaming > of the actual change, i.e. the CXL AER plumbing. They also increase the > size of the patch set, making it more difficult to review. > > >>> +++ b/include/uapi/linux/pci_regs.h >>> @@ -73,6 +73,8 @@ >>> #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ >>> #define PCI_CLASS_DEVICE 0x0a /* Device class */ >>> >>> +#define PCI_CLASS_CODE_MASK __GENMASK(23, 8) >>> + >>> #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ >>> #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ >>> #define PCI_HEADER_TYPE 0x0e /* 8 bits */ > Putting this in a uapi header means we'll have to support it > indefinitely. Usually such macros are added to kernel-internal > headers first and moved to uapi headers if/when the need arises. > > Thanks, > > Lukas Apologies for the late response. The PCI_CLASS_CODE_MASK definition move to include/uapi/linux/pci_regs.h was requested here: https://lore.kernel.org/linux-cxl/6881626a784f_134cc7100b4@dwillia2-xfh.jf.intel.com.notmuch/ Would you like this patch removed altogether?  Terry