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([2a02:810d:15c0:828:7467:56f4:40b7:cba8]) by smtp.gmail.com with ESMTPSA id y7-20020a1709064b0700b00946be16f725sm5982854eju.153.2023.04.04.06.29.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 04 Apr 2023 06:29:11 -0700 (PDT) Message-ID: <63d456fa-4db5-96fc-107e-060e59754096@linaro.org> Date: Tue, 4 Apr 2023 15:29:10 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.0 Subject: Re: [PATCH v3 06/11] dt-bindings: PCI: Update the RK3399 example to a valid one Content-Language: en-US To: Rick Wertenbroek Cc: alberto.dassatti@heig-vd.ch, damien.lemoal@opensource.wdc.com, xxm@rock-chips.com, Shawn Lin , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Heiko Stuebner , Johan Jonker , Brian Norris , Caleb Connolly , Corentin Labbe , Judy Hsiao , Lin Huang , Arnaud Ferraris , Hugh Cole-Baker , linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20230404082426.3880812-1-rick.wertenbroek@gmail.com> <20230404082426.3880812-7-rick.wertenbroek@gmail.com> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 04/04/2023 10:58, Rick Wertenbroek wrote: > On Tue, Apr 4, 2023 at 10:45 AM Krzysztof Kozlowski > wrote: >> >> On 04/04/2023 10:24, Rick Wertenbroek wrote: >>> Update the example in the documentation a valid example. >>> The default max-outbound-regions is 32 but the example showed 16. >> >> This is not reason to be invalid. It is perfectly fine to change default >> values to desired ones. What is not actually obvious is to change some >> value to a default one, instead of removing it... > > Hello, the example value <0x0 0x80000000 0x0 0x20000>; is plain wrong > and will crash the kernel. This is a value that point to an address that falls > in the DDR RAM region but depending on the amount of RAM on the > board this address may not even exist (e.g., board with 2GB or less). We talk about max-outbound-regions. > > Also this address requires pointing to where the PCIe controller has the > windows from AXI Physical space to PCIe space. This address is > allocated when the SoC address map is created so it can only be that > one unless rockchip refabs the SoC with another address map. > > The example never worked with the values given as reported by e.g., > https://stackoverflow.com/questions/73586703/device-tree-issues-with-rockpro64-pcie-endpoint > and here they set it to 0 (base of the DDR, which is a "valid" address > as to it exists even on boards with less than 2GB) but it is still wrong > to do so. Again, my comment was under max-outbound-regions, not under some other pieces. Does this all apply? Best regards, Krzysztof