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[83.9.29.16]) by smtp.gmail.com with ESMTPSA id o19-20020ac24353000000b004dc4c5149cfsm769586lfl.134.2023.03.15.03.34.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 15 Mar 2023 03:34:15 -0700 (PDT) Message-ID: <6425fcb2-2ce9-0986-ed28-64717dee240a@linaro.org> Date: Wed, 15 Mar 2023 11:34:13 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH v4 05/18] PCI: qcom: Use lower case for hex Content-Language: en-US To: Manivannan Sadhasivam , andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com References: <20230315064255.15591-1-manivannan.sadhasivam@linaro.org> <20230315064255.15591-6-manivannan.sadhasivam@linaro.org> From: Konrad Dybcio In-Reply-To: <20230315064255.15591-6-manivannan.sadhasivam@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 15.03.2023 07:42, Manivannan Sadhasivam wrote: > To maintain uniformity, let's use lower case for representing hexadecimal > numbers. > > Signed-off-by: Manivannan Sadhasivam > --- To be fair, preprocessor defines are the only place where uppercase hex is widely used Konrad > drivers/pci/controller/dwc/pcie-qcom.c | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 926a531fda3a..4179ac973147 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -39,17 +39,17 @@ > #define PARF_PCS_DEEMPH 0x34 > #define PARF_PCS_SWING 0x38 > #define PARF_PHY_CTRL 0x40 > -#define PARF_PHY_REFCLK 0x4C > +#define PARF_PHY_REFCLK 0x4c > #define PARF_CONFIG_BITS 0x50 > #define PARF_DBI_BASE_ADDR 0x168 > -#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x16C /* Register offset specific to IP ver 2.3.3 */ > +#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x16c /* Register offset specific to IP ver 2.3.3 */ > #define PARF_MHI_CLOCK_RESET_CTRL 0x174 > #define PARF_AXI_MSTR_WR_ADDR_HALT 0x178 > -#define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8 > -#define PARF_Q2A_FLUSH 0x1AC > -#define PARF_LTSSM 0x1B0 > +#define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 > +#define PARF_Q2A_FLUSH 0x1ac > +#define PARF_LTSSM 0x1b0 > #define PARF_SID_OFFSET 0x234 > -#define PARF_BDF_TRANSLATE_CFG 0x24C > +#define PARF_BDF_TRANSLATE_CFG 0x24c > #define PARF_SLV_ADDR_SPACE_SIZE 0x358 > #define PARF_DEVICE_TYPE 0x1000 > #define PARF_BDF_TO_SID_TABLE_N 0x2000 > @@ -60,7 +60,7 @@ > /* DBI registers */ > #define AXI_MSTR_RESP_COMP_CTRL0 0x818 > #define AXI_MSTR_RESP_COMP_CTRL1 0x81c > -#define MISC_CONTROL_1_REG 0x8BC > +#define MISC_CONTROL_1_REG 0x8bc > > /* PARF_SYS_CTRL register fields */ > #define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN BIT(29)