From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4310B377A9C; Wed, 30 Sep 2026 10:19:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790763592; cv=none; b=UNjO0uCCUZ6wfNORNLzWjvevFah7Dc/WrPzrOQStrhBYPWEQ+Lv5QrpNwSkXgMiX+Eu9d8rvYpUsjvt97KZ0Tj7sgv8hha4HK3wJBLJ35KoHEg3orvvvfnzoSivfXFeyoWFghRAcSNIL1ITOgPoMWXbWZEbzLB/GsORDDedyDo4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790763592; c=relaxed/simple; bh=jJeVTal18ZboXas5TlF0vpQa6AGU2gJphl8DkP+LlWE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=H1keaB+LAtWMoYMFUEYf2vE8/bEQldl6jOq4wBIcQIjnSflyt1D1sp5rQtCFzTU5DhhrL+a1mylGVBWYnnxMAaVjqqfsgk8CuUeEBE9C7vbdu5/bIQRCGwAjFg23KBSji8SPUSc+2xza80/BFG2bUmhPyjjHyRmlNmiyEeS9X14= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=nNpZ6W6X; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="nNpZ6W6X" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Type:Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To; bh=jJeVTal18ZboXas5TlF0vpQa6AGU2gJphl8DkP+LlWE=; b=nNpZ6W6XiB5Nc5MTJcyBWGCqKX j6cKBfoDGI+MQo2ik+/teJHWq5My68+4ohp1EICY2XTXxoETiH5RxSOIKaYz5uwcM2Eb2A+uPeipm QtiyW5CYiCyIOjPZjqLy4HMSFCTKcm+EzdZJnODlw2RsZjvDgJHfSxa7PpiFtye5E6XNoebW9dP78 6uUC/gndnqMIgVFE4+oAywabv8gajwt1ppnkUA3FIlsNkAi6R1bp+oKw0mNfy9CP0lRaOjC3YVk8b ILpDVJhvdbWddVOiV9r2YTk4kjdnK/cZdlOkTuSBdboUBH+YFGOedYVL25tTLbaShqPw/irPKUBjb 1nRJGHOQ==; From: Heiko =?UTF-8?B?U3TDvGJuZXI=?= To: Vinod Koul , Manivannan Sadhasivam , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi , Brian Masney , Jerome Brunet , Michal Wilczynski Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Marek Szyprowski , Maud Spierings , Graham Markall , Icenowy Zheng , Chaoyi Chen , Joshua Peisach , Uwe =?UTF-8?B?S2xlaW5lLUvDtm5pZw==?= , Michal Wilczynski Subject: Re: [PATCH v5 11/21] drm/bridge: inno-hdmi: Add .mode_valid platform operation Date: Wed, 30 Sep 2026 12:19:15 +0200 Message-ID: <6458508.5fSG56mABF@diego> In-Reply-To: <20260929-jh7110-clean-send-v5-11-82b4d8e3c6c7@samsung.com> References: <20260929-jh7110-clean-send-v5-0-82b4d8e3c6c7@samsung.com> <20260929-jh7110-clean-send-v5-11-82b4d8e3c6c7@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Am Dienstag, 29. September 2026, 12:31:08 Mitteleurop=C3=A4ische Sommerzeit= schrieb Michal Wilczynski: > inno_hdmi_bridge_mode_valid() validates the pixel clock against > hdmi->refclk, but that clock is optional and is only present on > platforms that describe a "ref" clock. Platforms where the pixel clock > is produced by a separate device - such as the StarFive JH7110, whose > PHY is both the clock and the PHY provider - have no "ref" clock, so > the check is skipped entirely and every mode is reported as valid. >=20 > A mode the platform cannot generate is then advertised to userspace. > The subsequent modeset appears to succeed, since the atomic enable path > cannot fail, and the display silently stays blank. >=20 > Add a .mode_valid platform operation so platforms can reject modes they > are unable to drive. Platforms that do not implement it are unaffected. >=20 > Reviewed-by: Joshua Peisach > Signed-off-by: Michal Wilczynski In patch 19 you add the jh7110-inno-hdmi-phy variant of the phy which registers a clock provider for the pixel clock. Isn't that the refclk you're missing? Thanks Heiko