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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-66e02d36f16sm573732a12.3.2026.04.02.02.42.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 02 Apr 2026 02:42:28 -0700 (PDT) Message-ID: <6488e6e7-726c-4f0b-a6b0-2914b04e118a@oss.qualcomm.com> Date: Thu, 2 Apr 2026 11:42:26 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC 1/2] arm64: dts: qcom: eliza: Add display (MDSS) with Display CC To: Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa References: <20260331-dts-qcom-eliza-display-v1-0-856f0b66b282@oss.qualcomm.com> <20260331-dts-qcom-eliza-display-v1-1-856f0b66b282@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260331-dts-qcom-eliza-display-v1-1-856f0b66b282@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDAyMDA4NiBTYWx0ZWRfX7IdaZ7qUcv5q +G9Ws0XTkivSPLv4fbybobegbELBXLAdeqo19nBriWt64MGNeN/etW16xRhKswGcaGq/U9n33pq 5ugjRL5ccXpdKQ1sX/tfuXYY6OhLo09Va98UG0Jnxqokimae94jMMm2kZmwr3y78dj12syj+p0J UKJfcl21WDsPunkRe1s7MYD0e9JYrc3k9n5tuYrB8CT+DR9hqTdK+vmiBBxZnFYma/TWikQYM6M gPMzM42b3/F/jRhPUhBO9Ypp3FRdSlzbVxO6FJpLEIOgXaCsPZs9+ja2V03vDt5fBxbvHkDJ1V2 bqUDrB5zzWjTDH0leVHf5Wz6GVjukvEAfFNB+UTBWXSOlFv/aJ0iWHAYZJyGt7F5xkLkHiXpsrs 1PObREBxLoMv4TmOKGUCZuyW52s+dCfW6C0Sw8DCpQ3R3y1LvQUWyHmvbQr4ZZX9/K2nPkXvBxj IlR7CpXlotyWtJNo+/w== X-Proofpoint-GUID: _lDFaGG3LYPbjcHgRP9JIrLumAp7uC4g X-Proofpoint-ORIG-GUID: _lDFaGG3LYPbjcHgRP9JIrLumAp7uC4g X-Authority-Analysis: v=2.4 cv=e9ULiKp/ c=1 sm=1 tr=0 ts=69ce3a06 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=dN0IigM5nE1fyUEilRMA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-02_01,2026-04-02_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 phishscore=0 bulkscore=0 malwarescore=0 clxscore=1015 suspectscore=0 adultscore=0 spamscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2604020086 On 3/31/26 4:02 PM, Krzysztof Kozlowski wrote: > Add device nodes for almost entire display: MDSS, DPU, DSI, DSI PHYs, > DisplayPort and Display Clock Controller. > > Missing pieces are HDMI PHY and HDMI controller. > > Signed-off-by: Krzysztof Kozlowski > > --- [...] > + mdss_mdp: display-controller@ae01000 { > + compatible = "qcom,eliza-dpu"; > + reg = <0x0 0x0ae01000 0x0 0x93000>, > + <0x0 0x0aeb0000 0x0 0x2008>; sz=0x3000 [...] > + mdss_dsi0: dsi@ae94000 { > + compatible = "qcom,eliza-dsi-ctrl", "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl"; linebreak? > + reg = <0x0 0x0ae94000 0x0 0x400>; > + reg-names = "dsi_ctrl"; > + > + interrupts-extended = <&mdss 4>; > + > + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, > + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, > + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, > + <&dispcc DISP_CC_MDSS_ESC0_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>, > + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, > + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, > + <&dispcc DISP_CC_ESYNC0_CLK>, > + <&dispcc DISP_CC_OSC_CLK>, > + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, > + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; Why the source clocks? [...] > + mdss_dsi0_phy: phy@ae95000 { > + compatible = "qcom,eliza-dsi-phy-4nm", "qcom,sm8650-dsi-phy-4nm"; > + reg = <0x0 0x0ae95000 0x0 0x200>, > + <0x0 0x0ae95200 0x0 0x280>, sz=0x300 [...] > + mdss_dp0: displayport-controller@af54000 { > + compatible = "qcom,eliza-dp", "qcom,sm8650-dp"; > + reg = <0x0 0xaf54000 0x0 0x104>, please pad the addr to 8 hex digits sz=0x200 > + <0x0 0xaf54200 0x0 0xc0>, sz=0x200 > + <0x0 0xaf55000 0x0 0x770>, sz=0xc00 > + <0x0 0xaf56000 0x0 0x9c>, sz=0x400 > + <0x0 0xaf57000 0x0 0x9c>; sz=0x400 Also missing regs for quad-MST (Pixel2/3 @ 0x0af5_[89]000, each 0x400-long and MST2/3_link @ 0x0af5_[ab]000, 0x600-long). I don't know if the DPU can do quad-MST but there's registers.. Konrad