From: Kishon Vijay Abraham I <kishon@ti.com>
To: Yuti Amonkar <yamonkar@cadence.com>,
<linux-kernel@vger.kernel.org>, <dri-devel@lists.freedesktop.org>,
Maxime Ripard <maxime@cerno.tech>
Cc: <praneeth@ti.com>, <tomi.valkeinen@ti.com>, <jsarha@ti.com>,
<mparab@cadence.com>, <sjakhade@cadence.com>
Subject: Re: [PATCH v1] phy: Add DisplayPort configuration options
Date: Mon, 23 Dec 2019 18:06:17 +0530 [thread overview]
Message-ID: <64987727-12bd-ec92-ff80-0b3c330b12a3@ti.com> (raw)
In-Reply-To: <ca6d9a16-0cba-cde7-f60c-75305f88bf33@ti.com>
+ Maxime (Fixed Maxime's email address)
On 23/12/19 5:57 PM, Kishon Vijay Abraham I wrote:
> + Maxime
>
> Hi,
>
> On 23/12/19 12:24 PM, Yuti Amonkar wrote:
>> Allow DisplayPort PHYs to be configured through the generic
>> functions through a custom structure added to the generic union.
>> The configuration structure is used for reconfiguration of
>> DisplayPort PHYs during link training operation.
>>
>> The parameters added here are the ones defined in the DisplayPort
>> spec which include link rate, number of lanes, voltage swing
>> and pre-emphasis.
>
> Which version of display port specification?
>
> Rest of commit log should move below the "---"
>
>
>>
>> This patch was a part of [1] series earlier but we think that it needs
>> to have a separate attention of the reviewers. Also as both [1] & [2] are
>> dependent on this patch, our sincere request to reviewers to have a
>> faster review of this patch.
>>
>> [1]
>>
>> https://lkml.org/lkml/2019/12/11/455
>>
>> [2]
>>
>> https://patchwork.kernel.org/cover/11271191/
>
> Thanks
> Kishon
>
>>
>> Signed-off-by: Yuti Amonkar <yamonkar@cadence.com>
>> ---
>> include/linux/phy/phy-dp.h | 95
>> ++++++++++++++++++++++++++++++++++++++++++++++
>> include/linux/phy/phy.h | 4 ++
>> 2 files changed, 99 insertions(+)
>> create mode 100644 include/linux/phy/phy-dp.h
>>
>> diff --git a/include/linux/phy/phy-dp.h b/include/linux/phy/phy-dp.h
>> new file mode 100644
>> index 0000000..18cad23
>> --- /dev/null
>> +++ b/include/linux/phy/phy-dp.h
>> @@ -0,0 +1,95 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/*
>> + * Copyright (C) 2019 Cadence Design Systems Inc.
>> + */
>> +
>> +#ifndef __PHY_DP_H_
>> +#define __PHY_DP_H_
>> +
>> +#include <linux/types.h>
>> +
>> +/**
>> + * struct phy_configure_opts_dp - DisplayPort PHY configuration set
>> + *
>> + * This structure is used to represent the configuration state of a
>> + * DisplayPort phy.
>> + */
>> +struct phy_configure_opts_dp {
>> + /**
>> + * @link_rate:
>> + *
>> + * Link Rate, in Mb/s, of the main link.
>> + *
>> + * Allowed values: 1620, 2160, 2430, 2700, 3240, 4320, 5400, 8100
>> Mb/s
>> + */
>> + unsigned int link_rate;
>> +
>> + /**
>> + * @lanes:
>> + *
>> + * Number of active, consecutive, data lanes, starting from
>> + * lane 0, used for the transmissions on main link.
>> + *
>> + * Allowed values: 1, 2, 4
>> + */
>> + unsigned int lanes;
>> +
>> + /**
>> + * @voltage:
>> + *
>> + * Voltage swing levels, as specified by DisplayPort specification,
>> + * to be used by particular lanes. One value per lane.
>> + * voltage[0] is for lane 0, voltage[1] is for lane 1, etc.
>> + *
>> + * Maximum value: 3
>> + */
>> + unsigned int voltage[4];
>> +
>> + /**
>> + * @pre:
>> + *
>> + * Pre-emphasis levels, as specified by DisplayPort
>> specification, to be
>> + * used by particular lanes. One value per lane.
>> + *
>> + * Maximum value: 3
>> + */
>> + unsigned int pre[4];
>> +
>> + /**
>> + * @ssc:
>> + *
>> + * Flag indicating, whether or not to enable spread-spectrum
>> clocking.
>> + *
>> + */
>> + u8 ssc : 1;
>> +
>> + /**
>> + * @set_rate:
>> + *
>> + * Flag indicating, whether or not reconfigure link rate and SSC to
>> + * requested values.
>> + *
>> + */
>> + u8 set_rate : 1;
>> +
>> + /**
>> + * @set_lanes:
>> + *
>> + * Flag indicating, whether or not reconfigure lane count to
>> + * requested value.
>> + *
>> + */
>> + u8 set_lanes : 1;
>> +
>> + /**
>> + * @set_voltages:
>> + *
>> + * Flag indicating, whether or not reconfigure voltage swing
>> + * and pre-emphasis to requested values. Only lanes specified
>> + * by "lanes" parameter will be affected.
>> + *
>> + */
>> + u8 set_voltages : 1;
>> +};
>> +
>> +#endif /* __PHY_DP_H_ */
>> diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
>> index 15032f14..ba0aab5 100644
>> --- a/include/linux/phy/phy.h
>> +++ b/include/linux/phy/phy.h
>> @@ -16,6 +16,7 @@
>> #include <linux/pm_runtime.h>
>> #include <linux/regulator/consumer.h>
>> +#include <linux/phy/phy-dp.h>
>> #include <linux/phy/phy-mipi-dphy.h>
>> struct phy;
>> @@ -46,9 +47,12 @@ enum phy_mode {
>> *
>> * @mipi_dphy: Configuration set applicable for phys supporting
>> * the MIPI_DPHY phy mode.
>> + * @dp: Configuration set applicable for phys supporting
>> + * the DisplayPort protocol.
>> */
>> union phy_configure_opts {
>> struct phy_configure_opts_mipi_dphy mipi_dphy;
>> + struct phy_configure_opts_dp dp;
>> };
>> /**
>>
prev parent reply other threads:[~2019-12-23 12:34 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-23 6:54 Yuti Amonkar
2019-12-23 12:27 ` Kishon Vijay Abraham I
2019-12-23 12:36 ` Kishon Vijay Abraham I [this message]
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