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Mon, 07 Sep 2026 09:14:36 -0700 (PDT) X-Received: by 2002:a17:90a:51e6:b0:39b:4877:ae90 with SMTP id 98e67ed59e1d1-39b4877aeb8mr13830341a91.22.1788797676080; Mon, 07 Sep 2026 09:14:36 -0700 (PDT) Received: from [192.168.1.66] ([103.172.5.17]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3339bbf1feesm29345580eec.26.2026.09.07.09.14.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 07 Sep 2026 09:14:35 -0700 (PDT) Message-ID: <649f44a6-740b-46b3-86f4-990878ea0968@oss.qualcomm.com> Date: Mon, 7 Sep 2026 21:44:30 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] i2c: qcom-geni: Add support for I2C High-Speed mode To: Mukesh Savaliya , Vinod Koul , Frank Li , Viken Dadhaniya , Andi Shyti Cc: linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org References: <20260824-i2c-hs-v1-0-8dd94e5c6113@oss.qualcomm.com> <20260824-i2c-hs-v1-2-8dd94e5c6113@oss.qualcomm.com> <419902d5-cbb6-4d8f-acb6-d9640adb56d9@oss.qualcomm.com> Content-Language: en-US From: Jyothi Kumar Seerapu In-Reply-To: <419902d5-cbb6-4d8f-acb6-d9640adb56d9@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: rC7-dtMKmqPoNKI6sttGeCOCS_RuSIfb X-Authority-Analysis: v=2.4 cv=U+aiy+ru c=1 sm=1 tr=0 ts=6a9ee2ed cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=tPI8lZtLbYv5uT6OEmdSlg==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=oVe4sY28e3T6egSZGAoA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-GUID: rC7-dtMKmqPoNKI6sttGeCOCS_RuSIfb X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA3MDE4MCBTYWx0ZWRfXyfW/stcrcoXk FHa3S6+gZ0JeFCT21lKQfHQ2oaN6ACGw09I8QClph3asDiBm9jm7yB2QbWgZfvhsGMkXbm+xcky R55aPpJEKMm3h9L9yAi2s1I4mMHYq6U= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA3MDE4MCBTYWx0ZWRfXyjhftpAHrarO 1w6Vp2deW9XAzxXeBh00O1f18ubHwACCpM5+wSAChhtEXKaUw+ul9pQUSWrcPGEnEEcuij5smPC 6flYfcVF8m2lMmqGbl3wIVH7yvxK33AMT14cH9pNIybjOwAMX8Z4kzbnDLsNTqZqXZ7Dz4i0B5N S7WVggHaEr9B2U3/e0oBfm+yIvT+L4eW5tKQYfiSMBy+/FoMwB3q0kc33PX0vUzTa7P0DdJxdyW VlYaDankAq4m9So07WN1xfpCfVMvA5+m9LKMPOp/04krQ5VB80CkQV7rhyhPIDqSWiqx9nEZb0v ZRTkQg2386QjMBMeg8Xf6wO/19e8htQoiGN0w4FuPPX89jy79sBSuYYDyctaTzIIQzBTkUMiib1 rjS/Pz9ZcbZSwmATjs1ynDJ9ZqIWRE2ilXYkaaodD9s9aWtMGqhNHSxY5Bm5Yp4ok4ZgUvhmCSV KWW5eBpt4ctakCju05A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-07_04,2026-09-07_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 impostorscore=0 adultscore=0 bulkscore=0 spamscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609070180 On 8/28/2026 1:12 AM, Mukesh Savaliya wrote: > > Hi Mukesh, Thanks for the review comments.> On 8/24/2026 4:55 PM, Jyothi Kumar Seerapu wrote: > [...]>   struct geni_i2c_err_log { >> @@ -162,9 +180,14 @@ static const struct geni_i2c_err_log gi2c_log[] = { >>   struct geni_i2c_clk_fld { >>       u32    clk_freq_out; >>       u8    clk_div; >> -    u8    t_high_cnt; >> -    u8    t_low_cnt; >> -    u8    t_cycle_cnt; >> +    /* >> +     * In normal mode, these counter values fit within 8 bits. >> +     * In High-Speed mode, HS_TLOW_COUNT and HS_TCYCLE_COUNT are >> +     * 10-bit fields, so u16 is required. >> +     */ > Now, normal mode doesn't matter once switched to 16 bit. > May be comment also doesn't matter once change is merged, you can add > some information in commit log though. Will be taken as default size.> Sure, will remove these comments in V2.+ > u16    t_high_cnt; >> +    u16    t_low_cnt; >> +    u16    t_cycle_cnt; >>   }; >>   /* >> @@ -194,10 +217,30 @@ static const struct geni_i2c_clk_fld >> geni_i2c_clk_map_32mhz[] = { >>       {} >>   }; >> +/* source_clock = 100 MHz */ >> +static const struct geni_i2c_clk_fld geni_i2c_clk_map_100mhz[] = { >> +    { I2C_MAX_STANDARD_MODE_FREQ, 1, 449, 548, 998 }, >> +    { I2C_MAX_FAST_MODE_FREQ, 1, 76, 167, 248 }, >> +    { I2C_MAX_FAST_MODE_PLUS_FREQ, 1, 23, 59, 98 }, >> +    {} >> +}; >> + >>   static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c) >>   { >>       const struct geni_i2c_clk_fld *itr; >> +    /* Check if HS mode is requested */ >> +    if (gi2c->clk_freq_out == I2C_HS_MODE_FREQ) { >> +        gi2c->is_hs_mode = true; >> +        /* For HS mode, source clock should be 100 MHz */ >> +        itr = geni_i2c_clk_map_100mhz; >> +        /* For HS mode, start with 1MHz for master code */ >> +        gi2c->clk_fld = &itr[2]; >> +        return 0; >> +    } >> + > else part ? No, else is not required here, as the if condition for I2C HS mode case returns from the function. For non-HS mode case the below will execute. +    gi2c->is_hs_mode = false; >> + >>       if (clk_get_rate(gi2c->se.clk) == 32 * HZ_PER_MHZ) >>           itr = geni_i2c_clk_map_32mhz; >>       else >> @@ -219,7 +262,12 @@ static int qcom_geni_i2c_conf(struct geni_se *se, >> unsigned long freq) >>       const struct geni_i2c_clk_fld *itr = gi2c->clk_fld; >>       u32 val; >> -    writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL); >> +    if (gi2c->is_hs_mode) { >> +        writel_relaxed(I2C_HS_TCYCLE_CNT, gi2c->se.base + >> SE_I2C_HS_TCYCLE_REG); >> +        writel_relaxed(I2C_HS_TLOW_CNT, gi2c->se.base + >> SE_I2C_HS_TLOW_REG); >> +    } >> + >> +    writel_relaxed(gi2c->dfs_index, gi2c->se.base + SE_GENI_CLK_SEL); >>       val = (itr->clk_div << CLK_DIV_SHFT) | SER_CLK_EN; >>       writel_relaxed(val, gi2c->se.base + GENI_SER_M_CLK_CFG); >> @@ -500,7 +548,11 @@ static int geni_i2c_rx_one_msg(struct >> geni_i2c_dev *gi2c, struct i2c_msg *msg, >>           geni_se_select_mode(se, GENI_SE_FIFO); >>       writel_relaxed(len, se->base + SE_I2C_RX_TRANS_LEN); >> -    geni_se_setup_m_cmd(se, I2C_READ, m_param); >> + >> +    if (gi2c->is_hs_mode) > gi2c->is_hs_mode ? i2c->op = I2C_HS_READ : I2C_READ; > geni_se_setup_m_cmd(se, i2c->op, m_param);> + > geni_se_setup_m_cmd(se, I2C_HS_READ, m_param); >> +    else >> +        geni_se_setup_m_cmd(se, I2C_READ, m_param); >>       if (dma_buf && geni_se_rx_dma_prep(se, dma_buf, len, &rx_dma)) { >>           geni_se_select_mode(se, GENI_SE_FIFO); >> @@ -539,7 +591,11 @@ static int geni_i2c_tx_one_msg(struct >> geni_i2c_dev *gi2c, struct i2c_msg *msg, >>           geni_se_select_mode(se, GENI_SE_FIFO); >>       writel_relaxed(len, se->base + SE_I2C_TX_TRANS_LEN); >> -    geni_se_setup_m_cmd(se, I2C_WRITE, m_param); >> + >> +    if (gi2c->is_hs_mode) >> +        geni_se_setup_m_cmd(se, I2C_HS_WRITE, m_param); >> +    else >> +        geni_se_setup_m_cmd(se, I2C_WRITE, m_param); > same as above> Yes this can be set like below: geni_se_setup_m_cmd(se, gi2c->is_hs_mode ? I2C_HS_WRITE : I2C_WRITE, m_param); >>       if (dma_buf && geni_se_tx_dma_prep(se, dma_buf, len, &tx_dma)) { >>           geni_se_select_mode(se, GENI_SE_FIFO); >> @@ -700,7 +756,7 @@ static int geni_i2c_gpi(struct geni_i2c_dev *gi2c, >> struct i2c_msg msgs[], >>           goto out; >>       } > > [...] > >> @@ -1046,6 +1122,39 @@ static int geni_i2c_init(struct geni_i2c_dev >> *gi2c) >>           return ret; >>       } >> +    /* >> +     * For I2C High-Speed mode, first verify QUP HW version supports it >> +     * (requires QUPv3 core >= 4.3 per HPG), then configure 100 MHz >> source clock. >> +     */ > /* HS mode requires QUPv3 version >= 4.3 and source clock=100 MHz */ Sure, will update in V2.>> +    if (gi2c->is_hs_mode) { >> +        u32 hw_ver = geni_se_get_qup_hw_version(&gi2c->se); >> +        u32 major = GENI_SE_VERSION_MAJOR(hw_ver); >> +        u32 minor = GENI_SE_VERSION_MINOR(hw_ver); >> + >> +        if (major < QUP_I2C_HS_MIN_MAJOR || >> +            (major == QUP_I2C_HS_MIN_MAJOR && minor < >> QUP_I2C_HS_MIN_MINOR)) { >> +            dev_err(gi2c->se.dev, >> +                "QUP HW v%u.%u does not support I2C HS mode (requires >> >= %u.%u)\n", >> +                major, minor, >> +                QUP_I2C_HS_MIN_MAJOR, QUP_I2C_HS_MIN_MINOR); > then why it entered into is_hs_mode condition ? Need to check QUP version only for I2C HS mode requests, for other I2C modes no need of QUP version check. > +            ret = - > EOPNOTSUPP; >> +            goto err; >> +        } >> + >> +        ret = geni_se_clk_freq_match(&gi2c->se, I2C_HS_SRC_CLK_FREQ, >> +                         &gi2c->dfs_index, &freq_out, false); >> +        if (ret) { >> +            dev_err(gi2c->se.dev, "Failed to get DFS index for HS >> mode: %d\n", ret); >> +            goto err; >> +        } >> + >> +        ret = clk_set_rate(gi2c->se.clk, freq_out); >> +        if (ret) { >> +            dev_err(gi2c->se.dev, "Failed to set HS mode clock rate: >> %d\n", ret); >> +            goto err; >> +        } >> +    } >> + >>       proto = geni_se_read_proto(&gi2c->se); >>       if (proto == GENI_SE_INVALID_PROTO) { >>           ret = geni_load_se_firmware(&gi2c->se, GENI_SE_I2C); >> >