From: Dan Williams <dan.j.williams@intel.com>
To: Terry Bowman <terry.bowman@amd.com>, <alison.schofield@intel.com>,
<vishal.l.verma@intel.com>, <ira.weiny@intel.com>,
<bwidawsk@kernel.org>, <dan.j.williams@intel.com>,
<dave.jiang@intel.com>, <Jonathan.Cameron@huawei.com>,
<linux-cxl@vger.kernel.org>
Cc: <terry.bowman@amd.com>, <rrichter@amd.com>,
<linux-kernel@vger.kernel.org>, <bhelgaas@google.com>
Subject: Re: [PATCH v8 00/14] cxl/pci: Add support for RCH RAS error handling
Date: Fri, 30 Jun 2023 17:20:02 -0700 [thread overview]
Message-ID: <649f71329689f_14494294cc@dwillia2-mobl3.amr.corp.intel.com.notmuch> (raw)
In-Reply-To: <20230630231635.3132638-1-terry.bowman@amd.com>
Terry Bowman wrote:
> This patchset enables CXL RCH error handling. This is necessary because RCH
> downstream port protocol error handling is implemented uniquely and not
> currently supported. These patches address the following:
>
> * Discovery and mapping of RCH downstream port AER registers.
>
> * AER portdrv changes to support CXL RCH protocol errors.
>
> * Interrupt setup specific to RCH mode: enabling RCEC internal
> errors and disabling root port interrupts.
>
> Changes in V8:
> - Rebased onto: commit
> 0c0df63177e3 ("Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxl")
> - cxl/port: Pre-initialize component register mappings
> - Added patch to pre-initialize component register mappings.
> - cxl/pci: Remove Component Register base address from
> - Separated removal of Component Register base address in struct
> cxl_dev_state to not break functionality.
> - cxl/hdm: Use stored Component Register mappings to map HDM decoder
> capability
> - Implemented a less strict check in devm_cxl_setup_hdm(), be tolerant
> if HDM decoder registers are not implemented.
> - cxl/pci: Map RCH downstream AER registers for logging protocol errors
> - Fixed uninitialized access of map->dev in cxl_dport_map_regs().
> - PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem
> dev handler
> - Fix typo in patch description.
> - cxl/pci: Update CXL error logging to use RAS register address
> - Fix typo in patch description.
Hey Terry, thank you for turning this around so quickly. I will have a
look and see if this is suitable as a follow-up merge for v6.5 next week
since it would be nice to finish this off this cycle, but no promises.
prev parent reply other threads:[~2023-07-01 0:20 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-30 23:16 Terry Bowman
2023-06-30 23:16 ` [PATCH v8 01/14] cxl/port: Pre-initialize component register mappings Terry Bowman
2023-07-03 11:29 ` Jonathan Cameron
2023-06-30 23:16 ` [PATCH v8 02/14] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state Terry Bowman
2023-06-30 23:16 ` [PATCH v8 03/14] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability Terry Bowman
2023-07-04 0:39 ` Dan Williams
2023-07-14 17:46 ` Robert Richter
2023-08-08 3:00 ` Dan Williams
2023-08-25 14:32 ` Robert Richter
2023-06-30 23:16 ` [PATCH v8 04/14] cxl/pci: Remove Component Register base address from struct cxl_dev_state Terry Bowman
2023-06-30 23:16 ` [PATCH v8 05/14] cxl/port: Remove Component Register base address from struct cxl_port Terry Bowman
2023-06-30 23:16 ` [PATCH v8 06/14] cxl/pci: Add RCH downstream port AER register discovery Terry Bowman
2023-06-30 23:16 ` [PATCH v8 07/14] PCI/AER: Refactor cper_print_aer() for use by CXL driver module Terry Bowman
2023-06-30 23:16 ` [PATCH v8 08/14] cxl/pci: Update CXL error logging to use RAS register address Terry Bowman
2023-06-30 23:16 ` [PATCH v8 09/14] cxl/pci: Map RCH downstream AER registers for logging protocol errors Terry Bowman
2023-06-30 23:16 ` [PATCH v8 10/14] cxl/pci: Add RCH downstream port error logging Terry Bowman
2023-06-30 23:16 ` [PATCH v8 11/14] cxl/pci: Disable root port interrupts in RCH mode Terry Bowman
2023-06-30 23:16 ` [PATCH v8 12/14] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler Terry Bowman
2023-06-30 23:16 ` [PATCH v8 13/14] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Terry Bowman
2023-06-30 23:16 ` [PATCH v8 14/14] cxl/core/regs: Rename phys_addr in cxl_map_component_regs() Terry Bowman
2023-07-01 0:20 ` Dan Williams [this message]
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