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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b885b3dac6esm798364766b.7.2026.01.27.02.35.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 27 Jan 2026 02:35:31 -0800 (PST) Message-ID: <64e7cad1-cb7a-45f4-913e-bdceeaa42fc9@oss.qualcomm.com> Date: Tue, 27 Jan 2026 11:35:28 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v10 2/7] qcom-tgu: Add TGU driver To: Songwei Chai , andersson@kernel.org, alexander.shishkin@linux.intel.com, mike.leach@linaro.org, suzuki.poulose@arm.com, james.clark@arm.com, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, devicetree@vger.kernel.org, gregkh@linuxfoundation.org References: <20260109021141.3778421-1-songwei.chai@oss.qualcomm.com> <20260109021141.3778421-3-songwei.chai@oss.qualcomm.com> <54e3a23e-6426-445b-b5e4-43d727b88709@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <54e3a23e-6426-445b-b5e4-43d727b88709@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=OYOVzxTY c=1 sm=1 tr=0 ts=697894f4 cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=PdAv3VS2nydJPQNW2zsA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-GUID: 241PoFbHjbrzlrt7Iv8xfPyPn6rpuGSh X-Proofpoint-ORIG-GUID: 241PoFbHjbrzlrt7Iv8xfPyPn6rpuGSh X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTI3MDA4NiBTYWx0ZWRfX6W3f5GmCGTxI Uf6z9kencgA8Hl+GyyZ4sO5kHx7Kvw+bElCnPuv1PQLDVFdVMFrI4hOjYe9aG2AfAuW4ZUhz41l IrjacegB8vY/sGvRO4crHW68X7K6mEbSiiZz3C8yIgbdvLBOWHX94AqMe1a5BbfOqLXG8aKaeKT aFpDvJvvswScZ8KkLM4qYsi/2CUcvqDftxgGTOqwMXfAVc9t8WzaEr8C2Z9h8oKOdacK4ruKdIO p+D8zsiTolxolF5n5d9cbu/SxHSyJxQSNHNlVCl+lyAYjt5TS3ilbaw1Tco1G76GRGIRJ1ZlqrF l29CbfRiuoh8su7xholjWtZnvpjKLuKGdjbey/I+LTAaboLrMN13OLEAI79v1U9Yjc6y9T/jhsy cOkcQzjWbTK/QztMACbHYZaUMz/XEQrc8MsKACGN3X8y1vsZ2xf0EvNwZXhbKSb05sa15sTkxsV bma6DifFeOp9we+KvEQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.20,FMLib:17.12.100.49 definitions=2026-01-27_02,2026-01-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 adultscore=0 spamscore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 malwarescore=0 phishscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601270086 On 1/27/26 3:13 AM, Songwei Chai wrote: > Hi Konrad, > > Sorry for the late reply. > > On 1/13/2026 6:33 PM, Konrad Dybcio wrote: >> On 1/9/26 3:11 AM, Songwei Chai wrote: >>> Add driver to support device TGU (Trigger Generation Unit). >>> TGU is a Data Engine which can be utilized to sense a plurality of >>> signals and create a trigger into the CTI or generate interrupts to >>> processors. Add probe/enable/disable functions for tgu. >>> >>> Signed-off-by: Songwei Chai >>> --- [...] >>> +static inline void TGU_LOCK(void __iomem *addr) >>> +{ >>> +    do { >>> +        /* Wait for things to settle */ >>> +        mb(); >> >> What are we waiting for here? >> >>> +        writel_relaxed(0x0, addr + TGU_LAR); >> >> If you do a prompt TGU_LOCK()-TGU_UNLOCK() the writes may arrive in >> the order opposite to what you want, I'd say this shouldn't be _relaxed() >> and we should probably have a readback here to make sure the effect has >> taken place immediately >> >>> +    } while (0); >>> +} >>> + >>> +static inline void TGU_UNLOCK(void __iomem *addr) >>> +{ >>> +    do { >>> +        writel_relaxed(TGU_UNLOCK_OFFSET, addr + TGU_LAR); >>> +        /* Make sure everyone has seen this */ >>> +        mb(); >> >> I believe this should be a readback instead >> >>> +    } while (0); >>> +} > This lock/unlock sequence is intentionally modelled after the existing CoreSight CS_LOCK/CS_UNLOCK helpers, which have been in mainline for a > long time and are widely used on ARM systems. > > The barriers here are meant to provide CPU-side ordering guarantees > around the LAR access rather than to wait for the hardware lock/unlock > to complete. In particular, the intent is to prevent configuration > accesses from being reordered across the lock/unlock boundary, matching > the CoreSight programming model. > > I agree that the comments may be misleading in that regard, and I can > update them to clarify the ordering intent. > > If you still prefer a stricter write + readback sequence here, I’m also > happy to switch to that for additional conservatism. If the hardware doesn't mind potentially receiving commands in the locked state (i.e. they're not dropped), then this seems fine Otherwise, I think this may end up to random misconfigurations Konrad