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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b046cd5c274sm375616366b.98.2025.09.04.07.50.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 04 Sep 2025 07:50:05 -0700 (PDT) Message-ID: <6501e5b4-9939-4dac-991c-7a2033cfb506@oss.qualcomm.com> Date: Thu, 4 Sep 2025 16:50:02 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/5] i2c: qcom-cci: Add OPP table support and enforce FAST_PLUS requirements To: Konrad Dybcio , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Loic Poulain , Robert Foss , Andi Shyti Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org References: <20250904-topic-cci_updates-v1-0-d38559692703@oss.qualcomm.com> <20250904-topic-cci_updates-v1-4-d38559692703@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250904-topic-cci_updates-v1-4-d38559692703@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODMwMDAzMSBTYWx0ZWRfXyuiXVtQJ7Wod 92J9b34HbmAyZDWJYj2u8GDI9ktPoSQw6O7UL/wvO2Es1Zca5Okz0KqAmx366ohCaksmshfg4M0 ie2YCb1anu5R5QqL0O3kv2vY9tpzvv+69BoVf/QHHEOZOT6rTtTJHCoXzMV4HC3FV9+Ac324v3r HpfuhgfrvtK1oKUCRdC08si71VOVSUwisiJI6NSLX4QPihDtxtkxeOPT+TrVq58wUObSpVhs4k2 0QHFqtw3XKZWWqeaS9UK/w97UNa+8VGDM4np2anNl1PIJpx6salyTPvdfXMIS8Qo0NHBJj4Q/22 rcoNKCZilvDMecAV7uVqSL5h5NaI9QLOd4p17L28+/sm44VyRnqm3xwZ1S2HBIYPtxDKimwodkh PxXGsdej X-Authority-Analysis: v=2.4 cv=A8xsP7WG c=1 sm=1 tr=0 ts=68b9a727 cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=scFqH3SFngUqC7XewS8A:9 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-ORIG-GUID: wKxVpDQpIupGjNQ__YtshRFhnpDX_EJm X-Proofpoint-GUID: wKxVpDQpIupGjNQ__YtshRFhnpDX_EJm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-04_05,2025-09-04_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 impostorscore=0 bulkscore=0 clxscore=1015 suspectscore=0 malwarescore=0 priorityscore=1501 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508300031 On 9/4/25 4:31 PM, Konrad Dybcio wrote: > From: Konrad Dybcio > > The CCI clock has voltage requirements, which need to be described > through an OPP table. > > The 1 MHz FAST_PLUS mode requires the CCI core clock runs at 37,5 MHz > (which is a value common across all SoCs), since it's not possible to > reach the required timings with the default 19.2 MHz rate. > > Address both issues by introducing an OPP table and using it to vote > for the faster rate. > > Signed-off-by: Konrad Dybcio > --- > drivers/i2c/busses/i2c-qcom-cci.c | 33 +++++++++++++++++++++++++++++++++ > 1 file changed, 33 insertions(+) > > diff --git a/drivers/i2c/busses/i2c-qcom-cci.c b/drivers/i2c/busses/i2c-qcom-cci.c > index 74fedfdec3ae4e034ec4d946179e963c783b5923..d6192e2a5e3bc4d908cba594d1910a41f3a41e9c 100644 > --- a/drivers/i2c/busses/i2c-qcom-cci.c > +++ b/drivers/i2c/busses/i2c-qcom-cci.c > @@ -10,6 +10,7 @@ > #include > #include > #include > +#include > #include > > #define CCI_HW_VERSION 0x0 > @@ -121,6 +122,7 @@ struct cci_data { > struct i2c_adapter_quirks quirks; > u16 queue_size[NUM_QUEUES]; > struct hw_params params[3]; > + bool fast_mode_plus_supported; > }; > > struct cci { > @@ -466,9 +468,22 @@ static const struct i2c_algorithm cci_algo = { > .functionality = cci_func, > }; > > +static unsigned long cci_desired_clk_rate(struct cci *cci) > +{ > + if (cci->data->fast_mode_plus_supported) > + return 37500000ULL; > + > + return 19200000ULL; Well this is embarrassing ULL -> UL Konrad