Re: [PATCH] coresight: fix spelling in etm3x ABI documentation

[James Clark <james.clark@arm.com>]

On 10/07/2023 06:23, Randy Dunlap wrote:
> Correct spelling problems as identified by codespell.
> Correct one grammar error.
> 
> Fixes: 7a25ec8e481e ("coresight: Adding ABI documentation")
> Fixes: 7253e4c95616 ("coresight: etm3x: breaking down sysFS status interface")
> Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: James Clark <james.clark@arm.com>
> Cc: Leo Yan <leo.yan@linaro.org>
> Cc: coresight@lists.linaro.org
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> ---
>  Documentation/ABI/testing/sysfs-bus-coresight-devices-etm3x |   12 +++++-----
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 

Thanks for the fixes.

Reviewed-by: James Clark <james.clark@arm.com>

> diff -- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm3x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm3x
> --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm3x
> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm3x
> @@ -20,9 +20,9 @@ Date:		November 2014
>  KernelVersion:	3.19
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(RW) Used in conjunction with @addr_idx.  Specifies
> -		characteristics about the address comparator being configure,
> +		characteristics about the address comparator being configured,
>  		for example the access type, the kind of instruction to trace,
> -		processor contect ID to trigger on, etc.  Individual fields in
> +		processor context ID to trigger on, etc.  Individual fields in
>  		the access type register may vary on the version of the trace
>  		entity.
>  
> @@ -31,7 +31,7 @@ Date:		November 2014
>  KernelVersion:	3.19
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(RW) Used in conjunction with @addr_idx.  Specifies the range of
> -		addresses to trigger on.  Inclusion or exclusion is specificed
> +		addresses to trigger on.  Inclusion or exclusion is specified
>  		in the corresponding access type register.
>  
>  What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_single
> @@ -304,19 +304,19 @@ What:		/sys/bus/coresight/devices/<memor
>  Date:		September 2015
>  KernelVersion:	4.4
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
> -Description: 	(RO) Print the content of the ETM Trace Start/Stop Conrol
> +Description: 	(RO) Print the content of the ETM Trace Start/Stop Control
>  		register (0x018). The value is read directly from the HW.
>  
>  What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmtecr1
>  Date:		September 2015
>  KernelVersion:	4.4
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
> -Description: 	(RO) Print the content of the ETM Enable Conrol #1
> +Description: 	(RO) Print the content of the ETM Enable Control #1
>  		register (0x024). The value is read directly from the HW.
>  
>  What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmtecr2
>  Date:		September 2015
>  KernelVersion:	4.4
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
> -Description: 	(RO) Print the content of the ETM Enable Conrol #2
> +Description: 	(RO) Print the content of the ETM Enable Control #2
>  		register (0x01c). The value is read directly from the HW.