From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 94FB42E11DC for ; Wed, 15 Jul 2026 13:40:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784122842; cv=none; b=egmPdsNaobxTmUGrJjdzbaueN3CYLA4RlOnZpVs9aMWs78LV1go+leWbH1CijPn2GBT81jt43GyogsK5a3hYD4VliWoUSeH6n9/7EgElmKDPp+bRI9AwEHsAaS8y2ZRA3NzyfvVltN+yVC0RsobfXWB+IRLCzsvNT7NB+1jcQZ8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784122842; c=relaxed/simple; bh=o/mx+IN6C01zZLNimc1fWVcEnAB8uqWOfSp7yzRlGTQ=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=PHqufZEtjXsWUxCQC0Ocw7XkKMPSZ4ngEb+dG3+/aq6atFr14sYEs9W5AY3Oi1aOXFM4FwgUIKXxdUiwIU0dzhZL+HEsdDMZeir+Yi7ykHETjRz9CCVJ2aOnJLlyw96zrA21na9FD1Dq0ohFTw5X0DYW7KhVzM+btkl0e1XSz0g= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=h6HIF+R9; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="h6HIF+R9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1784122838; bh=o/mx+IN6C01zZLNimc1fWVcEnAB8uqWOfSp7yzRlGTQ=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=h6HIF+R9TYxE7aHeLmINbKqn5m4qofb1wYuAazpsR/fFZMfuod1n3QUNAp4zRG3Og SpkfqjciJ7Ku39dxKB1e5YbnT2jE+WAIKpFG41SUFb7sUoHSKNYI5ajah2DUYVtilB VYLbpqnuT6mawGrcQYTM3o1vqh+sMNbssoJfU+qP5Fd38fpv0ySDNBnPnCo0vLtkfD ToRQYRq6w0aLRrsMZKkiAQOJLtaOVRCkVHXGhgjWDzJTZYaIbewu6o3PxLgq5nn2BS /jiqkwMRd+xSbJ8e7Jy7cOT/zQ72nrX5+811Fl6OkHXzXHInnN5bNC8H6+jzMuyo3S +nsCNakXsDIAg== Received: from [100.64.1.21] (unknown [100.64.1.21]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id 3504517E0018; Wed, 15 Jul 2026 15:40:38 +0200 (CEST) Message-ID: <65558ccc-4f2c-492d-8c74-627d27dce864@collabora.com> Date: Wed, 15 Jul 2026 15:40:37 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] drm/mediatek: mtk_dsi: enable hs clock during pre-enable To: Gary Bisson Cc: Esben Haabendal , Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Matthias Brugger , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Adam Thiede , Thorsten Leemhuis References: <20260120-mtkdsi-v1-1-b0f4094f3ac3@gmail.com> <8733xko1ms.fsf@geanix.com> <0f719c00-3cf5-4403-afbf-713b07255981@collabora.com> From: AngeloGioacchino Del Regno Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 7/15/26 15:36, Gary Bisson wrote: > Hi, > > On Wed, Jul 15, 2026 at 03:25:11PM +0200, AngeloGioacchino Del Regno wrote: >> On 7/15/26 14:53, Esben Haabendal wrote: >>> Gary Bisson writes: >>> >>>> Some bridges, such as the TI SN65DSI83, require the HS clock to be >>>> running in order to lock its PLL during its own pre-enable function. >>>> >>>> Without this change, the bridge gives the following error: >>>> sn65dsi83 14-002c: failed to lock PLL, ret=-110 >>>> sn65dsi83 14-002c: Unexpected link status 0x01 >>>> sn65dsi83 14-002c: reset the pipe >>>> >>>> Move the necessary functions from enable to pre-enable. >>>> >>>> Signed-off-by: Gary Bisson >>> >>> Hi >>> >>> I have run into the same problem, but in combination with another >>> pipeline. I am seeing same problem with an i.MX8 using the nwl-dsi >>> bridge and the dcss driver. >>> >>> I have submitted a fix that adresses the problem in the ti-sn65dsi83 >>> driver instead. With a bit of luck, it can replace the fix proposed in >>> this thread. >>> >>> See https://lore.kernel.org/all/20260711-ti-sn65dsi83-fixes-v1-2-d85eb5342b98@geanix.com/ > > Thanks, just tried it on 7.2-rc3 with my patch reverted and confirm that > it works too. My assumption was that the SN65DSI83 was locking the PLL > earlier for some specific reason and therefore was reluctant to change > it. > >>> /Esben >> >> That clarifies a lot of things. >> >> The patch on mtk_dsi shall be reverted then. > > Angelo, do you want me to offer the revert patch? Should I wait to see > how the other thread goes? > Gary, yes please, send a revert and make sure to explain the reason why we're reverting this in the commit description :-) Cheers, Angelo