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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-33b510ff9a8sm3107175a91.8.2025.10.08.04.30.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 08 Oct 2025 04:30:57 -0700 (PDT) Message-ID: <6563611c-b7da-49b2-822b-79c5c5c67237@oss.qualcomm.com> Date: Wed, 8 Oct 2025 17:00:53 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 03/24] arm64: dts: qcom: Introduce Glymur base dtsi and CRD dts To: Marc Zyngier Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250925-v3_glymur_introduction-v1-0-24b601bbecc0@oss.qualcomm.com> <20250925-v3_glymur_introduction-v1-3-24b601bbecc0@oss.qualcomm.com> <867bxm1y8j.wl-maz@kernel.org> Content-Language: en-US From: Pankaj Patil In-Reply-To: <867bxm1y8j.wl-maz@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDA0MDAzNyBTYWx0ZWRfX7QmqDCuC0ejp vOMqeAeE5vFhiBGydgDe7FpElfk/sOxxL4iJfA2xTq3uoomPJ3jTmTiS9nmvJtWUpTv/LDqJTZj mwN8/sG66OVyDIXKvhylJTzsf2tnaZSHXJLwDcPoOEqgqOVSodGCImll5hXPHKmNRTXqG9zTKBA 6rU1A1FF56X+YPCUMOOFC0P1FJ64whHPktuVw4jK0RtJhB0jCieL4v8hpZIXVuf3JiWZqh8sf4q AiGrR3kjhO78jwTGSe6YFrp6VSpBO4NMmmw5Zf4nanWSGfQy0Bz6u6+2B5VERC/Ima0M1X2MKwh HstH7alQNEwZlQuWlb2XYLRuWBnMgk42VMyrMbdpjWtwD/tb3hxwXu2qK5vHXgLBE93jrfuFcvC bnE4yF5kqGoGnOvvKuU9GCObrdFBIw== X-Proofpoint-ORIG-GUID: qzGTrsSk15msqsRhJhAhsP07AVTDy7I4 X-Authority-Analysis: v=2.4 cv=WIdyn3sR c=1 sm=1 tr=0 ts=68e64b73 cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=EUspDBNiAAAA:8 a=mQOHZLyPYVvQyi9y9SsA:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-GUID: qzGTrsSk15msqsRhJhAhsP07AVTDy7I4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-08_03,2025-10-06_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 bulkscore=0 spamscore=0 adultscore=0 clxscore=1015 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2509150000 definitions=main-2510040037 On 9/25/2025 6:32 PM, Marc Zyngier wrote: > On Thu, 25 Sep 2025 07:32:11 +0100, > Pankaj Patil wrote: >> Introduce initial device tree support for Glymur - Qualcomm's >> next-generation compute SoC and it's associated Compute Reference >> Device (CRD) platform. >> >> The dt describes CPUs, CPU map, GCC and RPMHCC clock controllers, >> geni UART, interrupt controller, TLMM, reserved memory, >> interconnects, SMMU, firmware scm, watchdog, apps rsc, RPMHPD, >> SRAM, PSCI and pmu nodes. >> >> Signed-off-by: Pankaj Patil >> --- >> arch/arm64/boot/dts/qcom/Makefile | 1 + >> arch/arm64/boot/dts/qcom/glymur-crd.dts | 25 + >> arch/arm64/boot/dts/qcom/glymur.dtsi | 1320 +++++++++++++++++++++++++++++++ >> 3 files changed, 1346 insertions(+) >> > [...] > >> + intc: interrupt-controller@17000000 { >> + compatible = "arm,gic-v3"; >> + reg = <0x0 0x17000000 0x0 0x10000>, >> + <0x0 0x17080000 0x0 0x480000>; >> + >> + interrupts = ; >> + >> + #interrupt-cells = <3>; >> + interrupt-controller; >> + >> + #redistributor-regions = <1>; >> + redistributor-stride = <0x0 0x40000>; > Drop these two properties. I assume that your GIC implementation is > compliant with the architecture, and doesn't need hand-holding. > >> + >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + >> + gic_its: gic-its@17040000 { >> + compatible = "arm,gic-v3-its"; >> + reg = <0x0 0x17040000 0x0 0x40000>; >> + >> + msi-controller; >> + #msi-cells = <1>; >> + }; >> + }; > [...] > >> + timer { >> + compatible = "arm,armv8-timer"; >> + interrupts = , >> + , >> + , >> + ; > You are missing at one interrupt here, as the CPUs have both secure > security state and FEAT_VHE (hint: the EL2 virtual timer also has an > interrupt, usually on PPI 12). > > M. > Will fix both nodes