From: Andrew Lunn <andrew@lunn.ch>
To: MD Danish Anwar <danishanwar@ti.com>
Cc: Andrew Lunn <andrew+netdev@lunn.ch>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Meghana Malladi <m-malladi@ti.com>,
Himanshu Mittal <h-mittal1@ti.com>,
linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org,
linux-kernel@vger.kernel.org, srk@ti.com,
Vignesh Raghavendra <vigneshr@ti.com>,
Roger Quadros <rogerq@kernel.org>
Subject: Re: [PATCH net v3] net: ti: icssg-prueth: Fix emac link speed handling
Date: Wed, 6 Aug 2025 17:47:06 +0200 [thread overview]
Message-ID: <65645f94-3a61-47fa-ad13-9daaf89e926c@lunn.ch> (raw)
In-Reply-To: <20250805173812.2183161-1-danishanwar@ti.com>
On Tue, Aug 05, 2025 at 11:08:12PM +0530, MD Danish Anwar wrote:
> When link settings are changed emac->speed is populated by
> emac_adjust_link(). The link speed and other settings are then written into
> the DRAM. However if both ports are brought down after this and brought up
> again or if the operating mode is changed and a firmware reload is needed,
> the DRAM is cleared by icssg_config(). As a result the link settings are
> lost.
>
> Fix this by calling emac_adjust_link() after icssg_config(). This re
> populates the settings in the DRAM after a new firmware load.
>
> Fixes: 9facce84f406 ("net: ti: icssg-prueth: Fix firmware load sequence.")
> Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
next prev parent reply other threads:[~2025-08-06 15:47 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-05 17:38 MD Danish Anwar
2025-08-06 15:47 ` Andrew Lunn [this message]
2025-08-08 19:30 ` patchwork-bot+netdevbpf
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