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Thu, 14 Aug 2025 10:59:14 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGIklnR5m9SKzdIwzPoNhD2QB7ecbzwEviH7LYbrbwUTVp3FSf4QzZ8WYzFNV2mqkqnebnf1g== X-Received: by 2002:a17:902:e78e:b0:242:460e:4ab8 with SMTP id d9443c01a7336-244586dbc4dmr58552725ad.46.1755194354475; Thu, 14 Aug 2025 10:59:14 -0700 (PDT) Received: from [192.168.0.195] ([49.204.31.133]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-241d1ef595esm354448525ad.13.2025.08.14.10.59.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 14 Aug 2025 10:59:14 -0700 (PDT) Message-ID: <657a4915-fc24-4e6e-bd28-4e122e66c97d@oss.qualcomm.com> Date: Thu, 14 Aug 2025 23:29:08 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 6/7] dt-bindings: clock: qcom: document the Glymur Global Clock Controller To: Bjorn Andersson Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250813-glymur-clock-controller-v4-v4-0-a408b390b22c@oss.qualcomm.com> <20250813-glymur-clock-controller-v4-v4-6-a408b390b22c@oss.qualcomm.com> <2ac5aaa8-18ba-466a-ba67-8212daf9c3b5@oss.qualcomm.com> Content-Language: en-US From: Taniya Das In-Reply-To: <2ac5aaa8-18ba-466a-ba67-8212daf9c3b5@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODEyMDExOSBTYWx0ZWRfX5mdrUGb/gjye 9LrTQ64zJGkVKEWixWc3jereBlwyKwHQi6oFrbWwEBPAuhqzNwGti/Wd2U2+UUqHhiBL+MGtLmo D98po48rol2qGfhXMVvzQF7PXCOM72SEsOaZciTQht0jK+xPPe7daga8Mm2UmZnf9CD5ovCNNjf POG1GybNqCelh9VoP5/fMT74Hf2C8mxVu0YuUK4cpm3ua/kmGW2+Ydck+1HFiBv5mlRfrV2ANcb l/A+kc3w0fpLiQtbVnjrOr0of0z+4/a0p4Brt/d1/Olu7pBEH3coR+LbKkx5j4LxtsNubxq3UTD /EgZjM/lQd/syyjMPhqYwZJ/4Q2i3y9IYUBvGHwXb97FKt54M3BC0Yt6CWvSozIamn+4B3kgzs6 QWDcSVay X-Proofpoint-GUID: h_ImjdeDqHZAlTxSBjOp7iZZfDNi-m32 X-Proofpoint-ORIG-GUID: h_ImjdeDqHZAlTxSBjOp7iZZfDNi-m32 X-Authority-Analysis: v=2.4 cv=d4b1yQjE c=1 sm=1 tr=0 ts=689e23f4 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=/kiP2gCwObMqexHosDfpNA==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=_CSq4AhyHEGRIHh0IXIA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-13_02,2025-08-14_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 spamscore=0 phishscore=0 adultscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508120119 >>> + - description: USB 2 Phy PIPEGMUX clock source >>> + - description: USB 2 Phy SYS PCIE PIPEGMUX clock source >>> + - description: PCIe 3a pipe clock >>> + - description: PCIe 4b pipe clock Bjorn, will fix this typo and the below one as well. >>> + - description: PCIe 4 pipe clock >>> + - description: PCIe 5 pipe clock >>> + - description: PCIe 6 pipe clock >>> + - description: PCIe 6b pipe clock Got this extra due to huge list of external clocks. >> >> When I look at the documentation, we seem to have pipe clocks for pcie >> 0, 1, 2, 3a, 3b, 4, 5, and 6. And this seems to better match the clock >> defines below as well... >> > > Bjorn, the PCIE 0, 1, 2 are connected to USB4 PHY 0/1/2 pcie pipe clock > source. > >> Can you please confirm that the inputs you have listed here are complete >> and correct? (It's not going to be possible to add things in the middle >> later and adding 0, 1, and 2 at the bottom will not sit well with my >> OCD). >> > > These are the complete list of external clocks and nothing else is required. > >> Regards, >> Bjorn >> >>> + - description: QUSB4 0 PHY RX 0 clock source >>> + - description: QUSB4 0 PHY RX 1 clock source >>> + - description: QUSB4 1 PHY RX 0 clock source >>> + - description: QUSB4 1 PHY RX 1 clock source >>> + - description: QUSB4 2 PHY RX 0 clock source >>> + - description: QUSB4 2 PHY RX 1 clock source >>> + - description: UFS PHY RX Symbol 0 clock source >>> + - description: UFS PHY RX Symbol 1 clock source >>> + - description: UFS PHY TX Symbol 0 clock source >>> + - description: USB3 PHY 0 pipe clock source >>> + - description: USB3 PHY 1 pipe clock source >>> + - description: USB3 PHY 2 pipe clock source >>> + - description: USB3 UNI PHY pipe 0 clock source >>> + - description: USB3 UNI PHY pipe 1 clock source >>> + - description: USB4 PHY 0 pcie pipe clock source >>> + - description: USB4 PHY 0 Max pipe clock source >>> + - description: USB4 PHY 1 pcie pipe clock source >>> + - description: USB4 PHY 1 Max pipe clock source >>> + - description: USB4 PHY 2 pcie pipe clock source >>> + - description: USB4 PHY 2 Max pipe clock source >>> + >>> +required: >>> + - compatible >>> + - clocks >>> + - '#power-domain-cells' >>> + >>> +allOf: >>> + - $ref: qcom,gcc.yaml# >>> + >>> +unevaluatedProperties: false >>> + >>> +examples: >>> + - | >>> + #include >>> + clock-controller@100000 { >>> + compatible = "qcom,glymur-gcc"; >>> + reg = <0x100000 0x1f9000>; >>> + clocks = <&rpmhcc RPMH_CXO_CLK>, >>> + <&rpmhcc RPMH_CXO_CLK_A>, >>> + <&sleep_clk>, >>> + <&usb_0_phy_dp0_gmux>, >>> + <&usb_0_phy_dp1_gmux>, >>> + <&usb_0_phy_pcie_pipegmux>, >>> + <&usb_0_phy_pipegmux>, >>> + <&usb_0_phy_sys_pcie_pipegmux>, >>> + <&usb_1_phy_dp0_gmux_2>, >>> + <&usb_1_phy_dp1_gmux_2>, >>> + <&usb_1_phy_pcie_pipegmux>, >>> + <&usb_1_phy_pipegmux>, >>> + <&usb_1_phy_sys_pcie_pipegmux>, >>> + <&usb_2_phy_dp0_gmux 2>, >>> + <&usb_2_phy_dp1_gmux 2>, >>> + <&usb_2_phy_pcie_pipegmux>, >>> + <&usb_2_phy_pipegmux>, >>> + <&usb_2_phy_sys_pcie_pipegmux>, >>> + <&pcie_3a_pipe>, <&pcie_4b_pipe>, Fix here. >>> + <&pcie_4_pipe>, <&pcie_5_pipe>, >>> + <&pcie_6_pipe>, <&pcie_6b_pipe>, Fix here as well. >>> + <&qusb4_0_phy_rx_0>, <&qusb4_0_phy_rx_1>, >>> + <&qusb4_1_phy_rx_0>, <&qusb4_1_phy_rx_1>, >>> + <&qusb4_2_phy_rx_0>, <&qusb4_2_phy_rx_1>, >>> + <&ufs_phy_rx_symbol_0>, <&ufs_phy_rx_symbol_1>, >>> + <&ufs_phy_tx_symbol_0>, >>> + <&usb3_phy_0_pipe>, <&usb3_phy_1_pipe>, >>> + <&usb3_phy_2_pipe>, >>> + <&usb3_uni_phy_pipe_0>, <&usb3_uni_phy_pipe_1>, >>> + <&usb4_phy_0_pcie_pipe>, <&usb4_phy_0_max_pipe>, >>> + <&usb4_phy_1_pcie_pipe>, <&usb4_phy_1_max_pipe>, >>> + <&usb4_phy_2_pcie_pipe>, <&usb4_phy_2_max_pipe>; >>> + #clock-cells = <1>; >>> + #reset-cells = <1>; >>> + #power-domain-cells = <1>; >>> + }; >>> + -- Thanks, Taniya Das