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Tue, 23 Jun 2026 08:50:22 -0700 (PDT) X-Received: by 2002:ac8:7e8a:0:b0:50b:5286:f756 with SMTP id d75a77b69052e-51a4f4d4c47mr51047741cf.6.1782229822025; Tue, 23 Jun 2026 08:50:22 -0700 (PDT) Received: from [192.168.120.170] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-697ee52f216sm32857a12.3.2026.06.23.08.50.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 23 Jun 2026 08:50:21 -0700 (PDT) Message-ID: <65873506-1a9a-40ec-ac67-60f61a0b4b4c@oss.qualcomm.com> Date: Tue, 23 Jun 2026 17:50:18 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/8] clk: qcom: dispcc-sm8450: Fix mdss clocks To: esteuwu@proton.me, Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rob Clark , Will Deacon , Robin Murphy , "Joerg Roedel (AMD)" , Vinod Koul , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org References: <20260622-sm8450-qol-v1-0-37e2ee8df9da@proton.me> <20260622-sm8450-qol-v1-1-37e2ee8df9da@proton.me> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260622-sm8450-qol-v1-1-37e2ee8df9da@proton.me> Content-Type: text/plain; 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Only mdss takeover was > possible, but screen had to be turned off first. > > OLE configuration may have been a misinterpretation... that's not > something that's done on the downstream driver. > > Changing disp_cc_mdss_mdp_clk_src from clk_rcg2_shared_ops to > clk_rcg2_shared_no_init_park_ops fixes this warning as well: [...] > drivers/clk/qcom/dispcc-sm8450.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/qcom/dispcc-sm8450.c b/drivers/clk/qcom/dispcc-sm8450.c > index 2e91332dd92a..b99d3eb5e195 100644 > --- a/drivers/clk/qcom/dispcc-sm8450.c > +++ b/drivers/clk/qcom/dispcc-sm8450.c > @@ -614,7 +614,7 @@ static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { > .parent_data = disp_cc_parent_data_5, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_shared_ops, > + .ops = &clk_rcg2_shared_no_init_park_ops, > }, > }; > > @@ -1824,8 +1824,8 @@ static int disp_cc_sm8450_probe(struct platform_device *pdev) > disp_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; > disp_cc_pll1.clkr.hw.init = &sm8475_disp_cc_pll1_init; > > - clk_lucid_ole_pll_configure(&disp_cc_pll0, regmap, &sm8475_disp_cc_pll0_config); > - clk_lucid_ole_pll_configure(&disp_cc_pll1, regmap, &sm8475_disp_cc_pll1_config); > + clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &sm8475_disp_cc_pll0_config); > + clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &sm8475_disp_cc_pll1_config); > } else { > clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); > clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config); This can also be fixed by migrating to use qcom_cc_driver_data, which takes a list of alpha PLLs to be configured, and thenthere's a switch-statement in clk-alpha-pll.c that always assigns the correct function Konrad