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([2402:7500:4ce:aeef:99fc:78aa:eebe:b7e0]) by smtp.gmail.com with ESMTPSA id 13-20020a170902c24d00b001cc307bcdbdsm4303356plg.211.2023.11.09.19.58.04 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 Nov 2023 19:58:07 -0800 (PST) Content-Type: text/plain; charset=us-ascii Mime-Version: 1.0 (Mac OS X Mail 11.5 \(3445.9.7\)) Subject: Re: [PATCH 06/12] RISC-V: crypto: add accelerated AES-CBC/CTR/ECB/XTS implementations From: Jerry Shih In-Reply-To: <20231109071623.GB1245@sol.localdomain> Date: Fri, 10 Nov 2023 11:58:02 +0800 Cc: Paul Walmsley , palmer@dabbelt.com, Albert Ou , herbert@gondor.apana.org.au, davem@davemloft.net, andy.chiu@sifive.com, greentime.hu@sifive.com, conor.dooley@microchip.com, guoren@kernel.org, bjorn@rivosinc.com, heiko@sntech.de, ardb@kernel.org, phoebe.chen@sifive.com, hongrong.hsu@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org Content-Transfer-Encoding: quoted-printable Message-Id: <659DE1CF-4F42-4935-9DFD-E127269CEC54@sifive.com> References: <20231025183644.8735-1-jerry.shih@sifive.com> <20231025183644.8735-7-jerry.shih@sifive.com> <20231102051639.GF1498@sol.localdomain> <39126F19-8FEB-4E18-B61D-4494B59C43A1@sifive.com> <20231109071623.GB1245@sol.localdomain> To: Eric Biggers X-Mailer: Apple Mail (2.3445.9.7) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Nov 9, 2023, at 15:16, Eric Biggers wrote: > On Tue, Nov 07, 2023 at 04:53:13PM +0800, Jerry Shih wrote: >> On Nov 2, 2023, at 13:16, Eric Biggers wrote: >>> On Thu, Oct 26, 2023 at 02:36:38AM +0800, Jerry Shih wrote: >>>> +static int ecb_encrypt(struct skcipher_request *req) >>>> +{ >>>=20 >>> There's no fallback for !crypto_simd_usable() here. I really like = it this way. >>> However, for it to work (for skciphers and aeads), RISC-V needs to = allow the >>> vector registers to be used in softirq context. Is that already the = case? >>=20 >> The kernel-mode-vector could be enabled in softirq, but we don't have = nesting >> vector contexts. Will we have the case that kernel needs to jump to = softirq for >> encryptions during the regular crypto function? If yes, we need to = have fallbacks >> for all algorithms. >=20 > Are you asking what happens if a softirq is taken while the CPU is = between > kernel_vector_begin() and kernel_vector_end()? I think that needs to = be > prevented by making kernel_vector_begin() and kernel_vector_end() = disable and > re-enable softirqs, like what kernel_neon_begin() and = kernel_neon_end() do on > arm64. Refer to commit 13150149aa6ded which implemented that behavior = on arm64. >=20 > - Eric The current kernel-mode-vector implementation, it only calls = `preempt_disable()` during vector context. So, we will hit nesting vector context issue from = softirq which also use kernel-vector. https://lore.kernel.org/all/20230721112855.1006-1-andy.chiu@sifive.com/ Maybe we could use the `simd_register_aeads_compat()` wrapping as x86 = platform first in a simpler way first. -Jerry=